Two Port USB 3.1 GEN II PCI Express Card

Anyone else ordered a 2 Port USB 3.1 GEN II (10Gbps) PCI Express Card 1 USB Type C and 1 USB Type A Port (USB 3.1 A + C) from AliExpress.com?
2portusb31pciecard
Seem like they have one on sale for $26.99 in 19 hours from now. Ok. Let’s buy one and see what we get – they say that it works with OS X 10.6 and greater.

Update: Here is a first benchmark with a Sandisk 64GB USB3.1 type C flash drive.
orico_pa31-ac_sandisk64gb
I only installed the card and connected the SATA power cable to it. I did not modify anything. Worked out of the box, but this flash drive does not support 10Gbps. To test that I first need a new generation II device, which I do not have at the moment.

Update-2: I found some interesting lines in the log:

kernel: (kernel) 000003.592134 PEGP@00000000: AppleUSBXHCI::createPorts: port 1 unsupported protocol USB 03.01
kernel: (kernel) 000003.615236 PEGP@00000000: AppleUSBXHCI::createPorts: created port 1

kernel: (kernel) 000003.615527 PEGP@00000000: AppleUSBXHCI::createPorts: port 2 unsupported protocol USB 03.01
kernel: (kernel) 000003.615633 PEGP@00000000: AppleUSBXHCI::createPorts: created port 2

kernel: (kernel) 000003.615887 PEGP@00000000: AppleUSBXHCI::createPorts: created port 3
kernel: (kernel) 000003.616282 PEGP@00000000: AppleUSBXHCI::createPorts: created port 4

This is not good. Time for a tiny SSDT. Here is mine:

DefinitionBlock ("ssdt_usb-iMac171.aml", "SSDT", 2, "APPLE ", "Xhci", 0x00001000)
{
    External (_SB_.PCI0.PEG0, DeviceObj)
    External (_SB_.PCI0.PEG0.PEGP, DeviceObj)

    Scope (\_SB.PCI0.PEG0)
    {
        Scope (PEGP)
        {
            Name (_STA, Zero)  // _STA: Status
        }

        Device (XHC2)
        {
            Name (_ADR, Zero)  // _ADR: Address

            Device (RHUB)
            {
                Name (_ADR, Zero)
                Device (SSP1)
                {
                    Name (_ADR, One)
                    Name (_UPC, Package (0x04)
                    {
                        0xFF, 
                        0x09, 
                        Zero, 
                        Zero
                    })

                    Name (_PLD, Package (0x01)
                    {
                        Buffer (0x10)
                        {
                            /* 0000 */    0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
                            /* 0008 */    0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                        }
                    })

                    Method (_DSM, 4, NotSerialized)
                    {
                        If (LEqual (Arg2, Zero))
                        {
                            Return (Buffer (One)
                            {
                                0x03
                            })
                        }
                        Return (Package (0x02)
                        {
                            "UsbCPortNumber", 
                            One
                        })
                    }
                }

                Device (SSP2)
                {
                    Name (_ADR, 0x2)
                    Name (_UPC, Package (0x04)
                    {
                        0xFF,
                        0x09,
                        Zero,
                        Zero
                    })

                    Name (_PLD, Package (0x01)
                    {
                        Buffer (0x10)
                        {
                            /* 0000 */    0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                            /* 0008 */    0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                        }
                    })

                    Method (_DSM, 4, NotSerialized)
                    {
                        If (LEqual (Arg2, Zero))
                        {
                            Return (Buffer (One)
                            {
                                0x03
                            })
                        }
                        Return (Package (0x02)
                        {
                            "UsbCPortNumber",
                            0x02
                        })
                    }
                }

                Device (HS01)
                {
                    Name (_ADR, 0x03)
                    Name (_UPC, Package (0x04)
                    {
                        0xFF, 
                        0x09, 
                        Zero, 
                        Zero
                    })

                    Name (_PLD, Package (0x01)
                    {
                        Buffer (0x10)
                        {
                            /* 0000 */    0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
                            /* 0008 */    0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                        }
                    })
                }

                Device (HS02)
                {
                    Name (_ADR, 0x04)
                    Name (_UPC, Package (0x04)
                    {
                        0xFF,
                        0x09,
                        Zero,
                        Zero
                    })

                    Name (_PLD, Package (0x01)
                    {
                        Buffer (0x10)
                        {
                            /* 0000 */    0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                            /* 0008 */    0x31, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
                        }
                    })
                }
            }
        }
    }
}

I may want/need to change my initial SSDT later on, but at least the errors are gone now.

Also. Note that my card is installed in the first/primary slot (PEG0) of the motherboard, but your card may – most likely – use another slot. In short; don’t forget to change the device name 😉

Update-3: And here is a screenshot of a Samsung T3 (500GB) device in action:
samsung_t3_500gb
This is not a second generation USB 3.1 device, but already quite a bit faster than the Sandisk that I used previously for testing. Also. When you are going to use some external M.2 B key enclosure, then keep in mind that it will be limited to 500~550 MB/Sec due to SATA. Which is not a whole lot faster.

A better option would be some RAID enclosure with two SATA devices, or a M.2 M key device (non-SATA). These two can, at least in theory, use the 10 Gbps (up to 6 Gbps for SATA) of the USB 3.1 Gen 2 port.

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53 thoughts on “Two Port USB 3.1 GEN II PCI Express Card

  1. As far as I know, Mac OS doesn’t support 3.1 gen 2 yet, except in the MacBook Pro 2016 in Sierra. Maybe this uses a third party driver? Don’t third party USB drivers usually have problems? See if you can get the driver from a support site first.

    • Good idea. Let me check that right away. Thanks!

      Update: The ASMedia ASM1142 controller drivers only support Mavericks and Yosemite. AsMedia has no plans to update the driver for El Capitan and/or Sierra.

      • The ASMedia ASM1142 is compliant with Intel eXtensible Host Controller Interface specification revision 1.1, so shouldn’t Apple’s drivers work (with some patches for device matching maybe)? Otherwise, what’s the point of being compliant?

        The chosen driver should support USB 3.1 gen 2 (10 Gbps). That doesn’t include the USB driver in El Capitan which recognizes the XHC of the Alpine Ridge controller, but only supports HighSpeed ports because the SuperSpeed ports report their speed as 10 Gbps which is not supported by that version of the USB driver.

  2. Sierra displays my ASUS USB 3.1 ports, and a my ASUS TB3/USB 3.1 card as USB 3.1 in System Profiler, but the TB does not work, and the USB 3.1 ports run USB 3.0 speeds.

    Perhaps you can work some software magic.

    • I also have the TB3 card on a X99 A II and have not managed to properly show on System profiler nor the 3.1 😦 although my board has integrated 3.1 but it only runs at 5Gbs with a 3.1 device.

    • That’s interesting that the USB 3.1 ports run at USB 3.0 speeds. Are you using Apple’s drivers or third party drivers? In El Capitan on my Gigabyte Z170X Gaming 7 motherboard, using Apple’s drivers, the ports will only work at USB 2.0 speeds. I should try Sierra one day…

      Are we sure the MacBook Pro 2016 has support for 10 Gbps USB 3.1 gen 2 speeds? If so, then how does that differ from your hardware? I wonder if your Sierra has the same drivers as the MacBook Pro 2016’s Sierra?

      I wonder if TB3 functionality requires device properties like those of the MacBook Pro 2016 that Pike listed here:
      https://pikeralpha.wordpress.com/2016/11/02/macbookpro131-device-properties/

      Currently in El Capitan, on my motherboard, TB3 devices work if they are plugged in before booting. What’s missing is hot-plug functionality and reporting in System Profiler.

  3. I just picked up a USB-C to USB-A cable (as Apple are having sales on those), but I’m having problems with the Alpine Ridge controller on my motherboard.

    Not detected means: Not showing up in IORegisteryExplorer, Audio in System Settings, and under the controller in System Information.

    Attaching a microphone:
    * before booting up: Microphone not detected.
    * before booting up, then sleep the system: Microphone not detected.
    * after booting up: Microphone detected.
    * after booting up, then sleep the system: Microphone not detected.

    Replugging the microphone after sleep: Microphone detected.

    So it is only detected (and working) if attached AFTER the system is already running.

  4. Regarding your Update-2, are you still talking about the ASMedia card? The log says “AppleUSBXHCI”. Does that mean the card is not using third party drivers? Or does that mean it’s not using an AsMedia chip? I asked about that in a previous comment.

    “unsupported protocol USB 03.01” means USB 3.1 specification according to section 7.2.2 of the eXtensible Host Controller Interface revision 1.1 document. This is information stored in the xHCI Extended Capabilities of the PCI MMIO space of the xHCI device.

    How does the SSDT fix that? Does the Apple driver ignore that issue when it sees a UsbCPortNumber property?

    Also in the xHCI Extended Capabilities is the speed defined as a mantissa and an exponent. In El Capitan, a system log message appears for 10 Gbps ports “AppleUSBXHCIPCI::createPorts: unsupported speed mantissa 10 exponent 3”. Do you not see that message when because you’re using Sierra?

    Does your SSDT fix still allow 10 Gbps speed?

    • Yes. This is the same board that I ordered, and no I did not install any third party drivers. No errors in Sierra with the SSDT, and there is a lot going on in the driver. Reading the values from the _UPC method being one of them.

      I am still waiting for my external exclosures (M2 and normal SSD’s) to arrive. Not that I would have had time to test any Super Speed Plus capable devices, due to the water damage at home that I need to fix first (we had some insane heavy rain in the south of Spain) but I hope to do that as soon as possible.

      • I didn’t think about that. You made an SSDT for a PCIe card. Does your SSDT replace anything from the PCIe card? Can a PCIe card have ACPI information in it’s Expansion ROM or affect the ACPI tables?

        I can imagine the SSDT would affect the driver if the driver was made to look at that info (maybe that info overrides some of the xHCI Extended Capabilities or the presence of that information means the driver doesn’t need to consider some of the information in the xHCI Extended Capabilities).

  5. Thanks as always for your curiosity Pike!

    I just modified your mini-SSDT for my ASUS X99 Deluxe II motherboard, but System Information still reports Up to 5Gbp/s. Does your system say “Up to 10Gbp/s” now?

    I have a USB 3.1 Type C device attached in the rear and it mounts and works fine, but at these USB 3.0 speeds.

    • Oh crap. I knew that I forgot something; I had an external enclose shipped to me for testing, and the one thing that I forgot was… well just that.

      There isn’t a whole lot of hardware that supports the full 10Gbps speed. The best one at the moment is the sanDisk Extreme 900 but I do not own one.

      My plan is to test some new external enclosures with my new MacBook Pro (15-inch early 2017) and then see what the hack is doing with it.

      Will keep you posted.

    • I purchased the card Mark linked, but System Profiler shows “Up to 5Gbp/s” just as the USB 3.1 ports do on the motherboard.

      No one at that link provided any visual proof that they have it running at 10Gb. Is anyone here able to provide any evidence to the contrary? Thanks!

      • I bought this card “StarTech.com 2-Port USB 3.1 (10Gbps) Card – 2x USB-C – PCIe (PEXUSB312C)“. I tested it in macOS Sierra 10.12.3 on a Hackintosh. It uses an Asmedia ASM1142 chip (pci1b21,1242). The Apple driver is “AppleUSBXHCIPCI”.

        I also bought a “OWC Mercury Elite Pro Dual mini USB 3.1 Gen 2” with two 6Gb/s SSDs.

        I have a Hackintosh with a built-in Intel AlpineRidge Thunderbolt 3 controller (pci8086,15b6) that has one Thunderbolt 3 port (USB-C) and a 3.1 gen 2 USB-A port. The Apple driver for this is “AppleUSBXHCIPCIAR”.

        When the Dual mini is connected to the Asmedia chip, it says “Up to 5 Gb/sec” in System Information.app, but when it’s connected to the AlpineRidge chip, it says “Up to 10 Gb/sec”.

        “Blackmagic Disk Speed Test” shows that the Dual mini can read and write more than 5 Gb/sec when connected to any of the USB 3.1 gen 2 ports (AlpineRidge USB-C, AlpineRidge USB-A, Asmedia USB-C). The AplineRidge can read about 836 MB/s, but the Asmedia does only up to 784 MB/s. This may be because 784 MB/s is getting close to the 1000 MB/s limit of the Asmedia chip’s PCIe 2.0 x2 link. There are newer Asmedia chips with higher bandwidth advertised for some motherboards. I don’t know if there are any PCIe cards based on those yet. The GIGABYTE AORUS motherboards have Asmedia ASM2142 chips which use PCIe x2 gen 3. Gen 3 doesn’t help old Apple Mac Pros but it’s good for newer PC’s that have few or none USB 3.1 gen 2 ports.

        In conclusion, the “AppleUSBXHCIPCI” driver works at up to 10 Gb/sec but only reports “Up to 5 Gb/sec”. If someone can find an example where “AppleUSBXHCIPCI” reports “Up to 10 Gb/sec” then let us know.

        Edit by Pike: Links to hardware added.

      • Thanks for the heads up. Please e-mail me (a link to) your IORegistryExplorer dump so that I can have a look at it.

        Edit: Your StarTech cards connects through PCIe 3×1 (see Industry Standards).

        OWC states: “Sustained speeds up to 738MB/s“. No word about this being read or write, but reading your comment here… that is not entirely correct.

        I would also like to know the specified UsbConnector properties on your USB card and Thunderbolt USB ports. What are they? 3?

      • You linked the PEXUSB311A1C. My card is the one with 2 USB-C ports, the PEXUSB312C. BTW, how do I add links in these comments? Is there a URL with instructions? I don’t see any options in the normal comment editing UI.

        The ASM1142 has the option of connecting via PCIe Gen3 x1 or PCIe Gen2 x2. Startech chose PCIe Gen2 x 2 because that is 1000 MB/s where PCIe Gen3 x1 is only 984.6 MB/s but would be only 500 MB/s if a user connected it to an older PC that only had PCIe Gen2. You can google “ASM1142 Data Sheet” and look at page “vii”.

        I couldn’t find a data sheet for ASM2142. There’s a short description at http://www.gigabyte.us/mb/aorus/connectivity with some cool pictures.

        For my performance numbers, I showed only the faster read numbers and I only used Blackmagic because it’s quick (I just wanted to show that the ports were capable of more than 5 Gb/s, so I didn’t spend a lot of time on benchmarks). The write numbers are slower (756 MB/s on AlpineRidge USB, and 710 MB/s on ASM1142). Different benchmarking utilities will give different numbers. I haven’t tried Windows yet.

        For the SSD’s, I’m using two 1TB “OWC Mercury EXTREME Pro 6G”.
        https://eshop.macsales.com/item/OWC/SSD7P6G960.

        I don’t know what you mean by “UsbConnector properties” or what “3” means in that context. Is that from the IO registry, System Information.app, DSDT, PCIe XHC capabilities, or something else?

        I’ve sent a Dropbox link to your yahoo address.

      • Ok. I fixed the link.

        Now. About the PCIe links. I checked the StarTech Technical Specifications / Industry Standards. That is where I found this: “PCI Express Base Specification Rev. 3.0“. Meaning that they do in fact use PCIe 3.0×1 Which is of course backwards compatible with previous revisions, so why do you think that StarTech is using PCIe 2×2? If that was the case, then the former text doesn’t make sense to me.

        Your UsbConnector setting in rehab mans injector kext are all set to “3” instead of “9” for the SSP1 ports. That is not correct. Also. The USBSpeed property shows me a “4” instead of the “5”. That is also not correct. You could try to inject this. Take a look at: /S*/L*/E*/IOUSBHostFamily.kext/C*/P*/AppleUSBHub.kext/C*/Info.plist

      • Marketing types that create those web pages don’t know how to convey technical information, so I wouldn’t trust what you read on those sites when they are vague.

        “PCI Express Base Specification Rev. 3.0” refers to the spec and not the card’s speed. The spec includes all the speeds up to 8 GT/s. The throughput numbers they list are for a single lane. I think they probably just copy and pasted that info from somewhere else.

        They neglect to mention how many lanes the card uses (electrically x2) and which of the 3 speeds are used by the card. Physically it is x4 as you can see in the pictures. Nobody would use a x4 physical card to implement an x1 link, because that would make the card not usable in any physical x1 slot, of which there are many in modern ATX motherboards (my GA-Z170X-Gaming 7 has three x1 slots).

        You can examine the IOPCIExpressLinkCapabilities and IOPCIExpressLinkStatus values in the IORegistry. The capabilities says the card can do max 5 GT/s x2. The status says the card is currently doing that same speed 5 GT/s x2. I wrote a script to parse those values from a file generated by the ioreg command line. I’ve sent a link.

        I plan on moving that card to my Mac Pro 280 which has two PCIe Gen 2 slots and two PCIe Gen 1 slots.

        The ioreg for when the Dual mini is connected to Asmedia says “USBSpeed” = 4.
        The ioreg for when the Dual mini is connected to AlpineRidge says “USBSpeed” = 5.
        I’m guessing USBSpeed is where Apple System Information gets the “Up to 5 Gb/sec” or “Up to 10 Gb/sec” strings, which I’ve said is wrong in the Asmedia case since the benchmark screenshot I included shows that it can do more than 5 Gb/sec. The “USBSpeed” property seems to be set only for USB devices, not for ports or controllers. It describes the speed of the device, and not the maximum speed of the port. So that’s something I wouldn’t try to inject.

        I use RehabMan’s USBInjectAll.kext unmodified. On my Hackintosh, I believe it only affects the XHC of the 100 series chipset (8086,a12f). None of those ports are named SSP1. I use the uia_exclude boot argument to exclude unused ports. RehabMan set all the UsbConnector values to 3 since he can’t know how each motherboard implements each port. In my case, I have four HS ports that are not capable of SS, so those should be changed to have a value of 0 but they seem to work just fine using a value of 3.

        I guess the UsbConnector values usually come from the DSDT, but are overridden by the kext. In my DSDT (unmodified), I searched for the method _UPC (USB Port Capabilities) which is described in the ACPI 6.1 spec. All the ports are set to type FF “Proprietary connector”.

        The AlpineRidge and Asmedia chips don’t have any _UPC methods. It is optional anyway.

        Is UsbConnector used anywhere? Does it change what System Information.app displays? Unless this affects something that a normal user would see (they may look at System Information.app, but probably not the io registry), then I don’t think it’s worth trying to correct. I know you made a DSDT with _UPC methods to remove some errors from the system log which I also would do but I don’t see those errors in my logs (or I don’t know how to see them in Sierra’s new Console.app) and you haven’t proved that those _UPC methods are necessary to remove the errors.

      • Sorry for asking this, but did you actually ask StarTech what is used? Instead of pure speculation. Next to that. I was referred to this piece of information:


        PCI Express Gen 1.0 max throughput is 2.5Gbps.
        PCI Express Gen 2.0 max throughput is 5Gbps.
        PCI Express Gen 3.0 max throughput is 10Gbps.

        You think that both of it is wrong? Based on what? Your script? That won’t work. Not for me. Not if you use the IORegistry data (as you do) because that will only shows you the Max Link Speed (5 GT/s) and the Link Width (x2). We only need that as indication of the supported maximum speed, of 10 Gbps for support USB 3.1 Gen. 2. It won’t tell you anything about the physical interconnect.

        About the _UPC object. Yes indeed. It is optional for the ACPI specification, but not to the Apple driver. Without these objects, the driver dumps errors. Using a tiny SSDT solved this problem.

        I did notice that you are using rehabman’s kext. I personally don’t. I want to know what I am doing, and what I can expect from it. Making errors is then also my own fault. Not that of someones else. This sometimes also helps me to learn something new again. I love to make errors. That is when you learn how not to do something.

        Now. About the UsbConnector property. Nowhere did I say that using some other value (than 3/255) would magically solve the reported connection speed in System Profiler. Nine is just the value that Apple is using, and what I am using. Next to that. The errors that were there before, are all gone with my tiny SSDT. To me that was enough. I’ll see what I can do this weekend, but I am busy with other stuff and well. I’m not making any promises.

        Edit:

        Heres are the defined connector types in the ACPI v6.0 specification:

        0x08 = Type C connector – USB2 only
        0x09 = Type C connector – USB2 and SS with Switch
        0x0A = Type C connector – USB2 and SS without Switch

        Apple is using 0x09 but we should probably use 0x0A for the ports on our PCIe cards.

      • LinkCapabilities is the max link width and speed supported by the card.

        LinkStatus is the negotiated link width and speed. This will be the same or less than the max link width and speed. For example (as stated in my comment January 19), this card in a PCIe gen 1 slot will have link speed 2.5 GT / s. This card in a slot that does not support x2 will have link width x1.

        I believe System Information.app gets the link width and speed information for PCI devices from the IOPCIExpressLinkStatus IO registry property (when you have the slot information set correctly in the device properties or DSDT which I have done yet).

        I’ve used lspci in Terminal.app to read the actual PCI registers and they match. I’ve also used PCIScope (http://www.tssc.de) in Windows (an awesome program for all things PCI). It agrees. They also make ACPIScope where you can see all the methods and actually execute some of them (such as _UPC). They have excellent customer support and will answer any questions and take suggestions. I can upload screen shots if you like.

        I’ll move the card to my Mac Pro 2008 during the weekend after I get Sierra installed on it. It does not have PCIe Gen 3 slots. I bought a Sonnet Tempo SSD Pro Plus because it is one of those rare SATA cards that actually uses x4 electrically (not just physically), so it should be as fast in a Gen 1 slot as the USB card will be in a Gen 2 slot.

        You have a similar USB card. Have you examined the link width and speed of that?

        I can’t find the errors that you found. Maybe I need to change a boot argument? If you tell me where you found the errors, then I’ll look. I can also share log files if you tell me which ones. I’m using macOS Sierra 10.12.3.

        I don’t see why using 9 instead of 3 should remove those errors since I have a USB type A port connected to the AlpineRidge that does support 10 Gb/sec. I included screen shots of the benchmark and the System Information.app for that case. The USB card in the image you posted also has a type A port which probably also supports 10 Gb/sec.

      • Of course I checked the values. I usually do that before posting/replying to people. Take a look at this example from my late 2016 MacBook Pro (15-inch):

        IOPCIExpressCapabilities….: Number 0x2
        IOPCIExpressLinkCapabilities: Number 0x455c41
        IOPCIExpressLinkStates……: Number 0x1041

        Note: Values copied from IORegistryExplorer, for a 10Gbps link (XHCI device).

        Link negotiations start at 2.5 GT/s (the 1 here is the Maximum Link Speed) and it stopped there. It found a Link Width of 4 (0x41 >> 4) and that is how it gets the supported 10 Gbps (4 x 2.5 GT/s).

        Another example. This time from a hack:

        IOPCIExpressCapabilities….: Number 0x2
        IOPCIExpressLinkCapabilities: Number 0x143d822
        IOPCIExpressLinkStates……: Number 0x1022

        Again. Link negotiations start at 2.5 GT/s (the 2 here is the Maximum Link Speed of 5 GT/s) and it stopped there. It found a Link Width of 2 (0x22 >> 4) and that is how it gets the supported 10 Gbps (2 x 5 GT/s).

        It’s that simple. I don’t need a script for that.

        I booted into single user mode, without my tiny SSDT, and immediately noticed this error:

        PEGP@00000000: AppleUSBXHCI::createPorts: port 2 unsupported protocol USB 03.01

        This is with the latest Beta of macOS Sierra and thus the error is still there. I copied the text from the log file.

        Also. Like I said before. I need a tiny SSDT to get rid of the errors. Nowhere did I say that using 0x09 is required. What I said was that 0x03 is wrong… for the USB Type C connectors (of a PCIe card with USB Type C connectors). See also my edit about the ACPI specification in one of my previous replies.

        Now. I also ordered the card that you are using, and I have used it, but I returned it. The reason for this is that is was slower than the Orico’s. Plural. Yes. Because I have two different models of this card. One with two USB Type C connectors, and the other with a USB Type C and USB A connector. The latter one is used for my blog.

        By the way. The SanDisk Extreme 900 1.9TB that I used should do 850Mbps (read speed) but I got 920 Mbps out of it. I only had it for a day or two before I had to return it, and that was why my update is still pending, because I do have news to share. When I am ready to share it with you.

      • Right, it is a simple script. I think the value of the script is that it does all the devices at once, so you can see all of the communication path from the root port down to your device across all the bridges. You don’t have to remember which bits are for link width and which are for link speed, and you don’t have to remember what the 3 link speed values are. The script also does all the bits, not just link width and speed (though I don’t know if those other bits are useful to us). I think the Device/Port Type of the IOPCIExpressCapabilities value is informative. It shows which devices are the upstream and downstream part of a bridge, and which devices are the endpoints, root ports, PCI-X bridges, etc.

        Clarification for link speed: The IOPCIExpressLinkStatus is not updated dynamically. Many devices like the Nvidia graphics card may idle at 2.5 GT/s, but may automatically switch speed to 8 GT/s when rendering 3D. So to get the current speed, you need to use something like lspci.

        Clarification for link width: Link width is a 6 bit number, so if the red digit in your examples is zero, then you need to look at the 3rd least significant digit modulo 4. If it’s 1, then the link width is x16. If it’s 2 then the link width is x32 (I’ve never seen an x32 slot or card).

        Your XHCI example is strange. Usually the devices of the motherboard chipset (or south bridge) don’t have PCI Express capabilities. For example, my Hackintosh’s io registry doesn’t have link status for the 100 series chipset XHC but does have them for the XHC of the Thunderbolt 3 chip (AlpineRidge), the Asmedia chip, and for the Fresco Logic chip in the Thunderbolt 2 Dock. It’s the same with my MacBook Pro (Mid 2015) MacBookPro11,5.

        I think you meant MacBook Pro (2016), because there is no Late 2015 Mac Book Pro. And the 2015 MacBook Pro doesn’t have 10 Gb/sec USB. In that case, you’re probably looking at the USB part of a Thunderbolt 3 chip. Maybe the pci8086,15b6, same as my hackintosh?

        I wonder why Orico’s card is faster. What were the speeds you measured? What benchmark did you use? Don’t they use the same Asmedia chip, link width, and link speed, and driver? Do they have the same latency numbers (from io registry)? You used the same PCI slot to test both? It’s possible for a USB 3 device to negotiate as a USB 2 device if there’s a problem with the connection. System Information.app will tell you the USB speed of the connection.

        I tested the Asmedia card in my Mac Pro 2008 running macOS Sierra 10.12.3. It is definitely running at 5.0 GT/s x2.

      • You know that you are replying to “maleorderbride” instead of Pike?

        Oops. Yes indeed. My 2015 was a typo. Fixed. Thanks.

        About my XHC example being strange. It’s not. On a Mac, since SuperSpeed and SuperSpeedPlus is handles by Thunderbolt. Only HighSpeed and below are handles by a secondary xHCI device.

        The SPUSBReporter checks for a value between 0 and 4:

        0 = low_speed = LowSpeed = Up to 1.5 Mb/sec
        1 = full_speed = FullSpeed = Up to 12 Mb/sec
        2 = high_speed = HighSpeed = Up to 480 Mb/sec
        3 = super_speed = SuperSpeed = Up to 5 Gb/sec
        4 = super_speed_plus = SuperSpeedPlus = Up to 10 Gb/sec

        Values that are used to get the localised text from Localizable.strings.

        The USBSpeed property on the other hand is set by IOUSBHostFamily and here’s what Apple does:

        00000000000235fb callq 0x23600
        0000000000023600 movq (%r14), %rax
        0000000000023603 movq 0x280(%rax), %rbx
        000000000002360a movq %r14, %rdi
        000000000002360d callq *0xc40(%rax)
        0000000000023613 shrl $0x8, %eax
        0000000000023616 andl $0x7, %eax
        0000000000023619 leaq 0x1d823(%rip), %rsi ## literal pool for: "USBSpeed"
        0000000000023620 movl $0x20, %ecx
        0000000000023625 movq %r14, %rdi
        0000000000023628 movq %rax, %rdx
        000000000002362b callq *%rbx
        000000000002362d movq (%r14), %rax
        0000000000023630 movq 0x280(%rax), %rbx
        0000000000023637 movq %r14, %rdi
        000000000002363a callq *0xc40(%rax)
        0000000000023640 andl $0xf, %eax
        0000000000023643 leaq 0x1d802(%rip), %rsi ## literal pool for: "USBPortType"

        Now. When we reverse this, knowing that Apple has USBSpeed set to five (5) and a hack four (4), notice the shrl $0x8, %eax instruction there. So we are (probably) looking at bits 11:8 (with a value of 0x500 compared to 0x400) and then there is this andl $0x7, %eax. The seven (0x7) here happens to be the SpeedMask, and when is the SpeedMask used? From xHCI MMIO address + 0x600 (DeviceConfiguration).

        Also. To show you that the USBSpeed property is not involved. Try this patch in the IOUSBHostFamily binary:

        Search for:

        C1 E8 08 83 E0 07

        And replace it with:

        B8 05 00 00 00 90

        Run: sudo touch /S*/L*/Extensions and reboot. After that all USB devices will report “USBSpeed 5”. SPUSBReporter though will still say: “Up to 5 Gb/sec”. Meaning that this property is not our target.

        This has to be it. For now. Back to work.

  6. PCIe cards that have a x4 physical connector may actually be only x2 electrical connection. This includes many or all of the ASM1142 cards. Some PCIe controllers do not allow x2, and will negotiate as x1 instead.

    Slot 3 and 4 of the Mac Pro 2008 will negotiate any x2 card as x1. Those slots are PCIe 1.0, and at x1, they allow 250 MB/s. That’s faster than an HDD but less than half the speed of an SSD. It’s still much better than firewire or USB 2.0.

    Slot 1 and 2 of the Mac Pro 2008 are PCIe 2.0 and will negotiate x2, so they will allow 1000 MB/s.

    Any PCIe slot connected directly to a Sandy Bridge CPU (2nd Generation Core Processor Family Desktop CPU’s) will not negotiate x2, and at PCIe 2.0, will allow up to 500 MB/s for x1. That’s almost as fast as an SSD.

    I would like to see a card that does PCIe 1.0 x4 so I can get the full performance of USB 3.1 on my old Mac Pro 2008 without using slot 1 (where the graphics card goes) or slot 2. For the ASM1142, the manufacturer would have to add a PCIe bridge chip to convert the PCIe 2.0 x2 of the ASM1142 to PCIe 1.0 x4 of the PCIe slot.

  7. I was replying to maleorderbride so that my reply would follow your reply which does not have a Reply button because the web page does not allow more than 2 levels of replies (to limit indenting?). This time, I’ll use the Leave a Reply edit box which will put this at the end of the web page.

    The Thunderbolt chip also does LowSpeed, FullSpeed, and HighSpeed. In my io registry, it has both AppleUSB20XHCIPort and AppleUSB30XHCIPort connected to AppleUSBXHCIAR. Isn’t your MacBook Pro 2016 the same? I’m guessing that for the MacBook Pro 2016, since all the external ports are Thunderbolt 3, the 100 series chipset XHCI controller is not used except for the built-in devices (keyboard, trackpad, webcam, touch bar…)

    The code you posted appears to be from IOUSBHostDevice::start(IOService*). 0x280(%rax) is this:
    bool IOUSBHostDevice::setProperty(const char *, long long unsigned int, unsigned int)
    And I think 0xc40(%rax) is this:
    uint32_t IOUSBHostDevice::getPortStatus()
    (I didn’t try using a debugger. I have a script to dump the fields and vtables of all the objects in the kernel development kit)

    I’m not sure where you got 0x600 DeviceConfiguration from. They’re not listed in the intel “eXtensible Host Controller Interface for Universal Serial Bus (xHCI) Revision 1.1” pdf document. I think you have to follow getPortStatus to know where the bits come from. Maybe you did that already.

    Anyway, IOUSBHostDevice::start is only called once. Maybe the speed changes after that? I don’t know what bits to check, and I don’t think lspci has access to MMIO?

    • I’m on my way out. It have to be brief. Another ultra short reply. Sorry.

      Why getStatus? Wouldn’t getSpeed be a better candidate, since it is using a SpeedMask?
      What you could do is set eax in getSpeed to 4 or 5 and see what you get, but the value used there is stuffed in from another piece of code.

      No. XHC2 (the Thunderbolt one) on my MacBook Pro is using so called companion ports:

      UsbCompanionLS
      UsbCompanionFS
      UsbCompanionHS

      – UsbCompanionPortNumer (Number) 08 00 00 00
      – UsbCompanionComtrollerName (String) XHC1

      XHC1 also, but then for SuperSpeed and SuperSpeedPlus:

      UsbCompanionSS
      UsbCompanionSSP

      – UsbCompanionPortNumer (Number) 04 00 00 00
      – UsbCompanionComtrollerName (String) XHC2

      They all link a port with a controller. The XHC1 ports also have a UsbCPortNumber property (set to 1 and 2).

      Apple’s Internal Keyboard and Trackpad is controlled by AppleIntelLpssSpiController

      Edit: The Intel Linux source code does a read from xHCI MMIO address + 0xc700 – 0xc100 (hello 0x600) to get the speed. There it also uses the SpeedMask. I’ll try to add this to RevoBoot later today, and see what I get from it. Nope. Wrong hardware.

      About IOUSBHostDevice::start being called only once. Of course. See also IOUSBHostInterface::updateMatchingProperties()

  8. It’s getPortStatus, because that is the method in the vtable of IOUSBHostDevice at offset 0xc40. This is confirmed by the dwarf file in the kernel debug kit.
    /Library/Developer/KDKs/KDK_10.12.3_16D32.kdk/System/Library/Extensions/IOUSBFamily.kext.dSYM/Contents/Resources/DWARF/IOUSBFamily

    And also by the vtables in the __DATA segment __const section of the IOUSBHostFamily binary. You can find the address of the table by looking at any of the four constructors “IOUSBHostDevice::IOUSBHostDevice” or the “IOUSBHostDevice::MetaClass::alloc() const” method.

    From the information you provided, the thing you call “SpeedMask” is just a mask to extract the speed from the getPortStatus function result. Also, the same function result is used to set the “USBPortType” property. And in that case, you would call the number “0xF” a PortTypeMask?

    From your last edit that you crossed out, I assume you got the terms “SpeedMask” and “DeviceConfiguration” from the Intel Linux source code?

    Minor correction: the SpeedMask 7 is only 3 bits wide, so the bits being looked at is 10:8, not 11:8

    Following the code further:
    uint32_t IOUSBHostDevice::getPortStatus() {
    rax = (*(**(rdi + 0xa0) + 0x878))(*(rdi + 0xa0));
    return rax;
    }

    From the dwarf file, 0xa0 is the offset in the IOUSBHostDevice object for “(AppleUSBHostPort *) _port”.

    The problem with the dwarf files in the Kernel Debug Kit is that they don’t contain debug information from all the Apple source files and Apple doesn’t open source a lot of their drivers. AppleUSBHostPort is one of the classes not included. But we have the vtable from the binary which has 0x878 as ___cxa_pure_virtual.

    Since it’s virtual, we probably want to look at the objects in the AppleUSBXHCI binary since XHC is the controller we’re looking at. There are three classes:
    AppleUSBXHCIPort
    AppleUSB20XHCIPort
    AppleUSB30XHCIPort

    Their vtables all have at 0x878 this:
    AppleUSBXHCIPort::getPortStatus()

    That calls these functions in the AppleUSBXHCIPort vtable:
    + 0xa38: AppleUSBXHCIPort::getPortSC() const
    + 0xa50: AppleUSBXHCIPort::getPortSpeed() const

    I’ll stop there. I guess getPortSC gets the port type, and getPortSpeed gets the speed.

    IOUSBHostInterface::updateMatchingProperties() has code like this:

    if ((*(*rbx + 0x2b8))(rbx, "USBSpeed") == 0x0) {
    (*(*rbx + 0x280))(rbx, "USBSpeed", (*(*rbx + 0xb90))(rbx) >> 0x8 & 0x7, 0x20);
    }
    if ((*(*rbx + 0x2b8))(rbx, "USBPortType") == 0x0) {
    (*(*rbx + 0x280))(rbx, "USBPortType", (*(*rbx + 0xb90))(rbx) & 0xf, 0x20);
    }

    The IOUSBHostInterface has these in the vtable:
    + 0x2b8: OSObject * IORegistryEntry::getProperty(const char *) const
    + 0xb90: uint32_t IOUSBHostInterface::getPortStatus() const

    So it appears updateMatchingProperties only sets USBSpeed once also (when getProperty returns nil).

    IOUSBHostInterface::getPortStatus() just calls IOUSBHostDevice::getPortStatus() using this field in the IOUSBHostInterface object:

    + 0x1b8,[ 8] (IOUSBHostDevice *) _device

    About your MacBook Pro, I found a post online containing the ioregistry for a MacBookPro13,2. It has UsbCompanionControllerPresent = 1 for the two Thunderbolt controllers XHC2 and XHC3 and UsbCompanionPortPresent for the SSP1 and SSP2 for each of those. I didn’t get a full picture since the ioregistry dump was only of the Device Tree plane.

    I wonder what is the purpose of companion controllers and ports or how they even work? Is the Thunderbolt chip not capable of the lower speeds? I noticed that the device id (8086,15d4) is not the same as with my AlpineRidge chip in my Hackintosh (8086,15b6). Maybe XHC1 is more power efficient or has better performance since it’s part of the motherboard chipset? I don’t think XHC1 can do SuperSpeed+, but it should be able to do SuperSpeed so why doesn’t XHC1 have UsbCompanionSS? Maybe UsbCompanionSS and UsbCompanionSSP have to be on the same port? LS, FS, HS all use the USB 2.0 pins and SS and SS+ use the USB 3.1 pins so maybe the companion ports have to be divided like that?

    • Thanks, but I cannot use dwarf files. I would be in breach of a contract if I did – you have to tick a checkbox to agree with their license. I have to do this the hard way.

      I think that getPortSC() reads the Port Status and Control Register (PORTSC). See 5.4.8 on page 309 of xHCI for Universal Serial Bus Specification Revision 1.1

      The bits 13:10 points to a Protocol Speed ID. The so called PSI’s. A 4 is used for 5 GT/s and a 5 for 10 GT/s. If you do the math: (0x1N00 >> 8) && 7 = N. In our case this would be a 4 or 5. The same value that is used for the “USBSpeed” and “port-status” properties. Here are some example values for the latter:

      0x1300 = HighSpeed.
      0x1400 = SuperSpeed.
      0x1500 = SuperSpeedPlus.

      They match with what we see in the registry. Everything here is fine. The speed is there, but the SPUSBReporter fails to report it. There is the problem.

      Note: XHC1 does have UsbCompanionSS/UsbCompanionSSP but only for linked ports.

      p.s. I do not a lot of free time due to a family health related problems. I better blog about that soon…

      • Can’t use dwarf files? They are generated by the compiler and used by debuggers for their symbolic information. It’s like saying you can’t use gcc to compile C code. Apple provides these symbol files so developers can debug their kernel extensions. How do you create and debug a kernel extension? Who is “they” and what is the license for? Who’s contract? What checkbox?

        Maybe you don’t mean dwarf files specifically, but Apple’s developer program in general? There’s a “Apple Developer Agreement” with a checkbox that you need to click in order to download the kernel debug kit. Are you not signed up as an Apple Developer? How else do you get developer tools?

        We haven’t determined why a 10 Gb/sec device reports as 5 Gb/sec. The IO Registry contains an incorrect value for “USBSpeed” (4 instead of 5), and “port-status” (0x1400 instead of 0x1500). I suspect the value changes in the xHCI registers between the time the properties are set in the IORegistry and when the device is actually used.

        I think the following would be handy:

        1) A utility like lspci that can read registers from the MMIO so we can prove the values are correct in the XHC registers. Maybe the value changes depending on whether the device is idle or not.

        2) A utility to modify the io registry from the command line so we can test which value is used by System Information.app.

        3) A kernel extension to force the IO registry value to update properly.

        4) A comparison of the code used by AlpineRidge where the correct value is displayed, and Asmedia where the value is incorrect. If the code is the same, then a debug session to compare the execution flow.

        5) A test in Windows to see the xHCI values there using a utility like PCIScope and what is reported by the OS.

        But it’s a low priority for me, since the problem is only cosmetic.

      • I’m not going to comment on the debug/dwarf file issues. And for obviously reasons.

        Anyway. It’s really simple. It’s like I said on 27 February 2017 at 10:54 pm: “Wouldn’t getSpeed be a better candidate, since it is using a SpeedMask?“. Seriously. AppleUSBXHCIPort:getPortSpeed() is where the device speed comes from. Want some evidence? Ok. Fine. Take a look at this screenshot:
        USB 3.1 at 10GT/s
        See also my comment from March 2, 2017 at 2:32 pm where I said that getPortSC() reads the Port Status and Control Register (PORTSC). I also added a link to the Intel specification. The problem with the Orico PCIe card is that Apple expects a different readout, and that register is read-only.

        Patching it also takes care of the “port-status” and “USBSpeed” properties. Here is a simple POC:

        Search for..: B9 03 00 00 00
        Replace with: B9 04 00 00 00

        p.s. This is not the patch that we want to use. Of course not, but we are on the right track.

        Edit: getPortSC() reads mov rax, qword [rdi+0x398]
        and setPortSC() writes a value there so this is our next target.

  9. Let me summarize:

    At February 24, 2017 at 8:23 am, I guessed that System Information.app might get it’s speed from USBSpeed.

    At February 27, 2017 at 10:01 am, you showed that USBSpeed and USBPortType come from callq *0xc40(%rax). You also showed then that USBSpeed is not used to show the speed in System Information.app, by forcing USBSpeed to always be set to 5.

    At February 27, 2017 at 9:54 pm, I explained that 0xc40 is IOUSBHostDevice::getPortStatus(). I didn’t claim that it has anything to do with what System Information.app displays.

    At February 27, 2017 at 10:54 pm, you thought I was still talking about System Information.app. I did not do as you suggest and try to set getSpeed result to 5 to see if that would change System Information.app.

    At March 2, 2017 at 3:06 am, I was still going on about 0xc40, USBSpeed and USBPortType. But I did find that getPortStatus uses getPortSC and getPortSpeed.

    At March 2, 2017 at 2:32 pm you went into getPortSC (which is also used by getPortSpeed). I was confused by your statement “They match with what we see in the registry. Everything here is fine. The speed is there, but the SPUSBReporter fails to report it. There is the problem.” because the values we see in the registry are not fine (we see 4 for 5 Gb/sec instead of 5 for 10 Gb/sec). SPUSBReporter reports the same incorrect result (no matter if it gets the value from the registry or somewhere else).

    Finally, at March 4, 2017 at 4:25 pm, you showed that patching getPortSpeed changes what System Information.app displays. Since getPortSpeed is used by getPortStatus (as I’ve shown), your patch also corrects the values in the registry.

    I’m not sure what you mean by “The problem with the Orico PCIe card is that Apple expects a different readout, and that register is read-only.” Is it possible the card is enumerating the speeds differently, such that 10 Gb/sec is 4? There is a table in the XHCi registers that lists the possible PSI’s, and maybe it has 4 as 10 Gb/sec? I should check PCIScope in Windows to see what those registers say.

    For the POC (what’s that acronym mean?) there is more than one occurrence of B9 03 00 00 00. Which function is the patch to be applied to?

    0x398 is a field in the AppleUSBXHCIPort class. setPortSC is in the vtable at 0xa48 so you can find who calls that by looking for 0xa48.

  10. I checked the registers of the Asmedia 1142 in Windows using PCIScope. The USB capabilities for both USB 2.0 and USB 3.0 don’t list port speeds (port speed count = 0). I don’t think this matters, as the Apple and Windows drivers don’t seem to require it. Fresco Logic 1100 and AlpineRidge both have the port speeds listed in the USB capabilities (of course, Fresco Logic 1100 doesn’t list speed 5 since it is only capable of SuperSpeed).

    I used PCIScope in Windows to watch the PORTSC registers of all 4 ports (2 for USB 2.0, 2 for USB 3.0). I connected and disconnected the USB 3.1 gen 2 raid multiple times. 50% of the time it would be USB 2.0 speed 3, another 50% of the time it would be USB 3.0 speed 4. Sometimes it would say speed 5. So I know it’s possible for the register to show speed 5. I’ve not been able to see that in macOS though.

    I updated the firmware of the Asmedia card from 150707_30_02_00 to 150707_30_02_0C but that made no difference.

    From this one might conclude that the raid device or USB cable are flaky, but the AlpineRidge controller has no problem determining the speed of the device. I watched those PORTSC registers as well, and they always showed the correct speed of 5.

    In macOS, I watched the port-status value in IORegistryExplorer, but I don’t know if that value reflects the current value of the PORTSC register all the time or only when the device is connected. We don’t know that the register is not changing after the property is set.

    You’ve said that System Information.app reads the current speed from the register using the result of getPortSpeed, but you haven’t determined when getPortSpeed is called in relation to when System Information.app calls for that information. Again, we don’t know that the register is not changing after getPortSpeed is called.

    So my suggestion for a utility in macOS to watch those registers would be useful here. If it is found that the register contains the correct value after getPortSpeed is called, then a possible patch would be to add some code to periodically update the registry properties. Or a delay could be introduced before the registry properties are set.

    I don’t think you’ve stated this explicitly yet, but have you experienced the same issues with your USB 3.1 gen 2 PCIe card and storage device? Specifically, that your benchmark tests of the device show more than 5 Gb/sec even though System Information.app says only “Up to 5 Gb/sec”? Have you had times where the device would connect as 480 Mb/sec?

    • I know that my Orico card is non-compliant, because PSIC is 0:

      7.2.2.1.2 Protocol Speed ID Count (PSIC) field

      USB xHCI Supported Protocol Capability data structures may define PSIC = ‘0’ field under the following conditions:
      • For a USB 3.0 xHCI Supported Protocol Capability data structure (i.e. Name String = 20425355h, Major Revision = 03h, and Minor Revision = 00h) a PSIC value of ‘0’ implies that only the default SuperSpeed bit rate is supported. Refer to Table 157 for default USB 3.0 Speed ID mappings.
      • For a USB 2.0 xHCI Supported Protocol Capability data structure (i.e. Name String = 20425355h, Major Revision = 02h, and Minor Revision = 00h) a PSIC value of ‘0’ implies that the default Full- speed, Low-speed, and High-speed bit rates are supported. Refer to Table 157 for default USB 2.0 Speed ID mappings.
      • Only these two protocols/revisions support implied mappings. All other protocols or revisions of these protocols shall define a non-zero PSIC value.

      USB 3.1 must specify a speed mapping, and set PSIC to a non-zero value. Ergo. This is a firmware issue that should be fixed by Asmedia or Orico.

      Edit: Take a look at this code snippet from the Linux xHCI source code:

      	/* Default Sublink Speed Attributes, overwrite if custom PSI exists */
      	0x34, 0x00, 0x05, 0x00,		/* 5Gbps, symmetric, rx, ID = 4 */
      	0xb4, 0x00, 0x05, 0x00,		/* 5Gbps, symmetric, tx, ID = 4 */
      	0x35, 0x40, 0x0a, 0x00,		/* 10Gbps, SSP, symmetric, rx, ID = 5 */
      	0xb5, 0x40, 0x0a, 0x00,		/* 10Gbps, SSP, symmetric, tx, ID = 5 */
      

      Note the 0x05 and 0x0a there. This value is checked by Apple. See the checks of register RBX. The USB revision (major) appears to be stored in register RSI with checks for 0x10, 0x20 and 0x30. By the way. It jumps at the check for 0x1E0.

      The port speed is a sticky value. It is set when the device is powered on.

      No problem here with the connection speed. Appears to be fine here.

  11. Hi Pike,
    I´m having problems when waking from sleep. I´m using ThunderboltEX3 on a Asus PRIME Z270 motherboard. After tuning your SSDT to fit my setup,I can boot without errors now. But when computer wakes from sleep, this is what i get spamming the console:

    kernel: (AppleUSBXHCIPCI) 000168.831138 XHC3@01000000: AppleUSBXHCIPCI::hardwareException: controller unplugged (PMCSR)
    kernel: (IOUSBMassStorageDriver) USB device 1307016501200000 – USBest Technology, USB Mass Storage Device – not found during wake up
    kernel: (AppleUSBXHCIPCI) 000169.052019 XHC3@01000000: AppleUSBXHCIPCI::hardwareException: controller unplugged (regRead32)
    kernel: (AppleUSBXHCI) 000169.052026 XHC3@01000000: AppleUSBXHCI::hardwareException: kUSBStatusControllerNotReady did not clear
    kernel: (IOUSBHostFamily) 000169.052030 XHC3@01000000: AppleUSBHostController::setPowerStateGated: going to state 2 failed with 0xe00002e9
    kernel: (AppleUSBXHCI) 000169.153080 HS02@01200000: AppleUSBXHCIPort::powerOn: deadline passed (PORTSC 0x00000000)
    kernel: (AppleUSBXHCI) 000169.153081 HS01@01100000: AppleUSBXHCIPort::powerOn: deadline passed (PORTSC 0x00000000)
    kernel: (AppleUSBXHCI) 000169.153087 SSP1@01300000: AppleUSBXHCIPort::powerOn: deadline passed (PORTSC 0x00000000)
    kernel: (AppleUSBXHCI) 000169.153088 SSP2@01400000: AppleUSBXHCIPort::powerOn: deadline passed (PORTSC 0x00000000)

    Could you please help me troubleshoot this error?
    Thank you very much.

    • Apple calls ACPI method _PS0 and _PS3 from the driver to enable/disable the controller. Perhaps something similar is required for your card.

      Note: kIOReturnDeviceError is defined as 0xe00002e9

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