XCPM for unsupported Processor…

The lack of XCPM support for my new Broadwell E processors was a bit frustrating and thus I had to do something about it. And I guess that most of you know me by now so it was just a matter of time. As in. Consider it done!

Yup. Time to say good-bye to the good old AppleIntelCPUPowerManagement.kext and the NullCPUPowerManagement.kext that served so many people for so long. Adieu my friends. They won’t be missed. LOL

Right. I can boot macOS Sierra and I see IOPPF: XCPM mode along with XCPM registered. That is pretty cool. In fact. This is amazing. Let’s go check some stuff.

sysctl -n machdep.xcpm.mode returns 1 so that is fine. Also. Running kextstat shows me that both AppleIntelCPUPowerManagement.kext and NullCPUPowerManagement.kext are missing in the list with loaded kexts. Great. Now a Geekbench v3.4.1 top score – one of four runs – of the Intel i7-6850K.

i7-6850K_macOS_Sierra_DP3_XCPM

I must admit. The longer I use this processor the more I get impressed by it. Who would have thought that? And let’s not forget. This is with XCPM so it is the more impressive. In fact. People with an old i7-5930K may keep it.

One thing though and that is that the RAM can’t run at full speed (runs like 2133MHz due to some bug) but anyway. Here is the output of AppleIntelInfo.kext

AppleIntelInfo.kext v1.5 Copyright © 2012-2016 Pike R. Alpha. All rights reserved

Settings:
------------------------------------
logMSRs............................: 1
logIGPU............................: 0
logCStates.........................: 1
logIPGStyle........................: 1
InitialTSC.........................: 0x150cbc299c8
MWAIT C-States.....................: 8480

Model Specific Registers
-----------------------------------
MSR_CORE_THREAD_COUNT......(0x35) : 0x6000C
MSR_PLATFORM_INFO..........(0xCE) : 0x20080C3BF3812400
MSR_PMG_CST_CONFIG_CONTROL.(0xE2) : 0x8402
MSR_PMG_IO_CAPTURE_BASE....(0xE4) : 0x10414
IA32_MPERF.................(0xE7) : 0x387EBCA78F
IA32_APERF.................(0xE8) : 0x3A56B9B06F
MSR_0x150..................(0x150) : 0x0
MSR_FLEX_RATIO.............(0x194) : 0xE0000
MSR_IA32_PERF_STATUS.......(0x198) : 0x23CF00002500
MSR_IA32_PERF_CONTROL......(0x199) : 0x2400
IA32_CLOCK_MODULATION......(0x19A) : 0x0
IA32_THERM_STATUS..........(0x19C) : 0x88490000
IA32_MISC_ENABLES..........(0x1A0) : 0x840089
MSR_MISC_PWR_MGMT..........(0x1AA) : 0x402000
MSR_TURBO_RATIO_LIMIT......(0x1AD) : 0x2525252525252828
IA32_ENERGY_PERF_BIAS......(0x1B0) : 0x1
MSR_POWER_CTL..............(0x1FC) : 0x2904005B
MSR_RAPL_POWER_UNIT........(0x606) : 0xA0E03
MSR_PKG_POWER_LIMIT........(0x610) : 0x7FFF80015FFF8
MSR_PKG_ENERGY_STATUS......(0x611) : 0x90C48C3
MSR_PKG_POWER_INFO.........(0x614) : 0x1700460
MSR_PP0_POWER_LIMIT........(0x638) : 0x0
MSR_PP0_ENERGY_STATUS......(0x639) : 0x0
MSR_PKGC6_IRTL.............(0x60b) : 0x0
MSR_PKG_C2_RESIDENCY.......(0x60d) : 0xA4268B844
MSR_PKG_C6_RESIDENCY.......(0x3f9) : 0x79FDD64350
IA32_TSC_DEADLINE..........(0x6E0) : 0x150CD144AC8

CPU Ratio Info:
------------------------------------
CPU Low Frequency Mode.............: 1200 MHz
CPU Maximum non-Turbo Frequency....: 3600 MHz
CPU Maximum Turbo Frequency........: 4000 MHz
CPU P-States [ 33 37 (40) ]
CPU C6-Cores [ 0 2 5 7 9 10 ]
CPU P-States [ 31 33 37 (40) ]
CPU C6-Cores [ 0 2 3 4 5 7 9 10 ]
CPU P-States [ (12) 31 33 37 40 ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 9 10 11 ]
CPU P-States [ (12) 25 31 33 37 40 ]
CPU P-States [ 12 25 29 31 33 37 (40) ]
CPU P-States [ 12 25 29 30 31 33 37 (40) ]
CPU P-States [ 12 25 28 29 30 31 33 37 (40) ]
CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 ]
CPU P-States [ (12) 22 25 28 29 30 31 33 37 40 ]
CPU P-States [ (12) 21 22 25 28 29 30 31 33 37 40 ]
CPU P-States [ (12) 21 22 23 25 28 29 30 31 33 37 40 ]
CPU P-States [ (12) 20 21 22 23 25 28 29 30 31 33 37 40 ]
CPU P-States [ 12 20 21 22 23 25 28 29 30 31 32 33 37 (40) ]
CPU P-States [ 12 20 21 22 23 25 28 29 30 31 32 33 37 39 (40) ]
CPU P-States [ 12 20 21 22 23 25 27 28 29 30 31 32 33 37 39 (40) ]
CPU P-States [ (12) 17 20 21 22 23 25 27 28 29 30 31 32 33 37 39 40 ]
CPU P-States [ (12) 16 17 20 21 22 23 25 27 28 29 30 31 32 33 37 39 40 ]
CPU P-States [ (12) 16 17 18 20 21 22 23 25 27 28 29 30 31 32 33 37 39 40 ]
CPU P-States [ 12 16 17 18 19 20 21 22 23 25 27 28 29 30 31 32 33 37 39 (40) ]
CPU P-States [ 12 16 17 18 19 20 21 22 23 25 27 28 29 30 31 32 33 37 38 39 (40) ]
CPU P-States [ 12 16 17 18 19 20 21 22 23 25 26 27 28 29 30 31 32 33 37 38 39 (40) ]
CPU P-States [ 12 16 17 18 19 20 21 22 23 25 26 27 28 29 30 31 32 33 36 37 38 39 (40) ]
CPU P-States [ (12) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 36 37 38 39 40 ]
CPU P-States [ 12 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 38 39 (40) ]
CPU P-States [ 12 14 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 38 39 (40) ]
CPU P-States [ (12) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 38 39 40 ]
CPU P-States [ 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]
CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 ]

Hmm. C3 is missing. Seems like I forgot to enable C3 for Broadwell E processors and thus I have to fix this and re-compile the kext. On a second thought. The redirection bits are not set in MSR 0xE2 so this is expected result.

But both MSR_PKG_C2_RESIDENCY and MSR_PKG_C6_RESIDENCY are non-zero. A sweet spot.

Update: I don’t have a lot of time, but I also do not want to let you wait so here you have it!

//
// kernel location 0x1fb451 (0xE9 in DP2/DP3/DP4, 0xF1 in DP1) _cpuid_set_info
//
// Broadwell E (0x4F)	-> Broadwell (0x47)	=> 0x4F-0x47 = 0x08	-> change 0xE9 into 0xE1
// Haswell E (0x3F)		-> Haswell (0x3C)	=> 0x3F-0x3C = 0x03	-> change 0xE9 into 0xE6
// Ivy Bridge E (0x3E)	-> Ivy Bridge (0x3A)	=> 0x3E-0x3A = 0x04	-> change 0xE9 into 0xE5

../..

//
// kernel location 0x22a422 (0xC4 in DP2/DP3/DP4, 0x?? in DP1) _xcpm_bootstrap
//
// Broadwell E (0x4F)	-> Broadwell (0x47)	=> 0x4F-0x47 = 0x08	-> change 0xC4 into 0xBC
// Haswell E (0x3F)		-> Haswell (0x3C)	=> 0x3F-0x3C = 0x03	-> change 0xC4 into 0xC1
// Ivy Bridge E (0x3E)	-> Haswell (0x3C)	=> 0x3E-0x3C = 0x02	-> change 0xC4 into 0xC2
//
// Broadwell E (0x4F)	-> Haswell (0x3C)	=> 0x4F-0x3C = 0x13	-> change 0xC4 into 0xB1

../..

//
// If MSR(0xE2) is locked (bit-15 is set) then also change
//
// kernel location 0x220b30 and 0x220b5f in _xcpm_idle from 0x0f30 (wrmsr) to 0x9090 (nop nop).

//
// Additionally (if booting results in a immediate reboot)
//
// kernel location 0x22a820 change 0x55 into 0xC3 (ret) to stop the KP.
//

Update: DP4 is now available and the byte patterns are still the same, but the locations have changed to: 0x1f8d81, 0x227d32, 0x21e440, 0x21e46f and 0x228130 (same order as above).

Update-2: DP5 is now available and the byte patterns are still the same, but the locations have changed to: 0x1f8930, 0x228af0, 0x21eff0, 0x21f01f and 0x228f50 (same order as above).

Update-3: DP6 is now available and the byte patterns are still the same, but the locations have changed to: 0x1f7cc0, 0x227f30, 0x21e430, 0x21e45f and 0x428390 (same order as above).

Update-4: DP7 is now available and the byte patterns are still the same, but the locations have changed to: 0x1f8d71, 0x227fc2, 0x21e460, 0x21e48f and 0x2283c0 (same order as above).

The patches can be done in at least three different ways and I picked what I think is the easiest one to understand. So I hope. Also. I don’t use FakeCPUID – nor Clover for that matter – with my patches, but some people using Clover reported a hang. For them it won’t boot without FakeCPUID (thanks to giacomoleopardo for the update).

Update: Owners of Ivy Bridge E or Haswell E processors do not need to patch the switch table used by _cpuid_set_info, because Apple already took care of it. Anyway. Have a look at this table:

switchtable_cpuid_set_info

The offset for the Broadwell E processor is missing in this table. There is an address but that jumps to a location for unsupported processors, which is why we need a patch for the Broadwell E processor (the red arrow shows you what we do with the patch) but I think that Apple will fix this with a future update of macOS Sierra so that we also no longer need to patch the table for Broadwell E processors.

Please note that the table was converted from the original one in the kernel, which looks like this:

0xffffff80003fbc6c	dd	0xfffff82c, 0xfffff831, 0xfffff831, 0xfffff7fb
0xffffff80003fbc7c	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff7fb
0xffffff80003fbc8c	dd	0xfffff7fb, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbc9c	dd	0xfffff831, 0xfffff831, 0xfffff809, 0xfffff831
0xffffff80003fbcac	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff810
0xffffff80003fbcbc	dd	0xfffff831, 0xfffff809, 0xfffff810, 0xfffff7fb
0xffffff80003fbccc	dd	0xfffff809, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbcdc	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbcec	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff817
0xffffff80003fbcfc	dd	0xfffff831, 0xfffff802, 0xfffff81e, 0xfffff817
0xffffff80003fbd0c	dd	0xfffff802, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbd1c	dd	0xfffff831, 0xfffff831, 0xfffff802, 0xfffff802
0xffffff80003fbd2c	dd	0xfffff81e, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbd3c	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff825
0xffffff80003fbd4c	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbd5c	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbd6c	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff831
0xffffff80003fbd7c	dd	0xfffff831, 0xfffff831, 0xfffff831, 0xfffff825

Update: DP4 is now available and while the table is still the same, the location of it has changed to: 0xffffff80003f959c

Update-2: DP5 is now available and while the table is still the same, the location of it has changed to: 0xffffff8000428cbc

Update-3: DP7 is now available and while the table is still the same, the location of it has changed to: 0xffffff80003f958c

And here is what I did with the values. Let’s take the last value (0xfffff825 ) as an example:

0xffffffff - (0xfffff825 - 0x01) = 0x7DB

I then used the value as a negative offset, and we do that because the table is located at a higher memory address, so here we go:

0xffffff80003fbc6c - 0x7DB = 0xffffff80003FB491

Great. Now look at this disassembled code snippet:

0xffffff80003fb43b	movzwl	0x6fcc42(%rip), %eax
0xffffff80003fb442	xorl	%ebx, %ebx				// Zero out %ebx
0xffffff80003fb444	movzbl	%al, %ecx
0xffffff80003fb447	cmpl	$0x6, %ecx				// Check CPU family
0xffffff80003fb44a	jne		0xffffff80003fb49d

0xffffff80003fb44c	movzbl	%ah, %eax
0xffffff80003fb44f	addl	$-0x17, %eax			// Lower model number (example: 0x5e -> 0x4f)
0xffffff80003fb452	cmpl	$0x47, %eax				// Check for unsupported model numbers
0xffffff80003fb455	ja		0xffffff80003fb49d		// Jump if greater than 0x47 (unsupported model numbers)

0xffffff80003fb457	leaq	0x80e(%rip), %rcx		// Store address of case table 0xffffff80003fbc6c into %rcx
0xffffff80003fb45e	movslq	(%rcx,%rax,4), %rax		// Move and sign-extend 32-bit value from switch table in %rax 
0xffffff80003fb462	addq	%rcx, %rax				// Example: 0xffffff80003fbc6c - 0x7db = 0xffffff80003fb491 (CPUFAMILY_INTEL_SKYLAKE)
0xffffff80003fb465	jmpq	*%rax					// Jump to target address

0xffffff80003fb467	movl	$0x6b5a4cd2, %ebx		// CPUFAMILY_INTEL_NEHALEM
0xffffff80003fb46c	jmp		0xffffff80003fb49d

0xffffff80003fb46e	movl	$0x10b282dc, %ebx		// CPUFAMILY_INTEL_HASWELL
0xffffff80003fb473	jmp		0xffffff80003fb49d

0xffffff80003fb475	movl	$0x573b5eec, %ebx		// CPUFAMILY_INTEL_WESTMERE
0xffffff80003fb47a	jmp		0xffffff80003fb49d

0xffffff80003fb47c	movl	$0x5490b78c, %ebx		// CPUFAMILY_INTEL_SANDYBRIDGE
0xffffff80003fb481	jmp		0xffffff80003fb49d

0xffffff80003fb483	movl	$0x1f65e835, %ebx		// CPUFAMILY_INTEL_IVYBRIDGE
0xffffff80003fb488	jmp		0xffffff80003fb49d

0xffffff80003fb48a	movl	$0x582ed09c, %ebx		// CPUFAMILY_INTEL_BROADWELL
0xffffff80003fb48f	jmp		0xffffff80003fb49d

0xffffff80003fb491	movl	$0x37fc219f, %ebx		// CPUFAMILY_INTEL_SKYLAKE
0xffffff80003fb496	jmp		0xffffff80003fb49d

0xffffff80003fb498	movl	$0x78ea4fbc, %ebx		// CPUFAMILY_INTEL_PENRYN
0xffffff80003fb49d	movl	%ebx, 0x6fcd35(%rip)
0xffffff80003fb4a3	cmpl	$0x0, 0x6fcb6e(%rip)
0xffffff80003fb4aa	je		0xffffff80003fb4c3

Our calculated address is spot on. Now let’s have a look at the switch table that is used by _xcpm_bootstrap in macOS Sierra DP3:

0xffffff800042a58c         dd         0xfffffeac, 0xfffffec7, 0xfffffeb8, 0xfffffeb8 
0xffffff800042a59c         dd         0xfffffeb8, 0xfffffeb8, 0xfffffeb8, 0xfffffeb8
0xffffff800042a5ac         dd         0xfffffeb8, 0xfffffed3, 0xfffffee9, 0xffffff0a
0xffffff800042a5bc         dd         0xfffffeb8, 0xfffffeb8, 0xfffffeb8, 0xfffffeb8
0xffffff800042a5cc         dd         0xfffffeb8, 0xfffffeb8, 0xffffff16, 0xfffffeb8
0xffffff800042a5dc         dd         0xfffffeb8, 0xfffffeb8, 0xfffffeb8, 0xfffffeb8
0xffffff800042a5ec         dd         0xfffffeb8, 0xfffffeb8, 0xfffffeb8, 0xfffffeb8
0xffffff800042a5fc         dd         0xfffffeb8, 0xfffffeb8, 0xfffffeb8, 0xfffffeb8
0xffffff800042a60c         dd         0xfffffeb8, 0xfffffeb8, 0xffffff2c

Update: DP4 is now available and while the table is still the same, the location of it has changed to: 0xffffff8000427e9c

Update: DP7 is now available and while the table is still the same, the location of it has changed to: 0xffffff800042812c

A shorter table with 34 instead of 72 values, but the idea here is the same. And with the same kind of table conversion we get this:

SwitchTable_xcmp_bootstrap

This time the table starts at 0x3c instead of 0x17 and there are no addresses for the Ivy Bridge E, Haswell E and Broadwell E processors, again, for the same reason; it jumps to a location for processors that do not support XCPM.

Speaking about that address. All locations in the switch table in the kernel with the value 0xfffffeb8 jump to the same location for unsupported processors and here is how to calculate the offset and target address for the jmp instruction:

0xffffffff - (0xfffffeb8-0x01) = 0x148
0xffffff800042a58c - 0x148 = 0xffffff800042a444

And looking at the disassembled code snipped of _xcpm_bootstrap that is where XCPM gets disabled:

0xffffff800042a420	addl	$-0x3c, %ebx					// Lower model number (example: 0x5e -> 0x22(34)
0xffffff800042a423	cmpl	$0x22, %ebx						// Check for unsupported models
0xffffff800042a426	ja		0xffffff800042a444				// Jump if greater than 0x22 (unsupported model numbers)

0xffffff800042a428	leaq	0x15d(%rip), %rax				// Store address of case table 0xffffff800042a58c into %rcx
0xffffff800042a42f	movslq	(%rax,%rbx,4), %rcx				// Move and sign-extend 32-bit value from switch table in %rax 
0xffffff800042a433	addq	%rax, %rcx						// Example: 0xffffff800042a58c - 0xd4 = 0xffffff80000x42a4b8 (Skylake)
0xffffff800042a436	jmpq	*%rcx							// Jump to target address

0xffffff800042a438	movl	$0x4, _xcpm_cpu_model(%rip)		// case 0: Haswell (0x3c-0x3c=0)
0xffffff800042a442	jmp		0xffffff800042a47f

0xffffff800042a444	movl	$0x0, _xcpm_mode(%rip)			// case 33: xcpm_mode = 0 (XCPM disabled)
0xffffff800042a44e	jmp		0xffffff800042a580

0xffffff800042a453	movl	$0x80, _xcpm_cpu_model(%rip)	// case 1: Broadwell (0x3d-0x3c=1)
0xffffff800042a45d	jmp		0xffffff800042a4ac

0xffffff800042a45f	movl	$0x10, _xcpm_cpu_model(%rip)	// case 9: Haswell-ULT (0x45-0x3c=9)
0xffffff800042a469	movl	$0x1, 0x602981(%rip)
0xffffff800042a473	jmp		0xffffff800042a47f

0xffffff800042a475	movl	$0x8, _xcpm_cpu_model(%rip)		// case 10: Crystalwell (0x46-0x3c=10)
0xffffff800042a47f	movl	$0x1, 0x602973(%rip)
0xffffff800042a489	movq	$0x0, 0x6029dc(%rip)
0xffffff800042a494	jmp		0xffffff800042a50c

0xffffff800042a496	movl	$0x40, _xcpm_cpu_model(%rip)	// case 11: Broadwell-H (0x47-0x3c=11)
0xffffff800042a4a0	jmp		0xffffff800042a50c

0xffffff800042a4a2	movl	$0x200, _xcpm_cpu_model(%rip)	// case 18: Skylake (0x4e-0x3c=18)
0xffffff800042a4ac	movl	$0x1, 0x60293e(%rip)
0xffffff800042a4b6	jmp		0xffffff800042a50c

0xffffff800042a4b8	movq	0x6cebf1(%rip), %rdi			// case 34: Skylake (0x5e-0x3c=34)
0xffffff800042a4bf	testq	%rdi, %rdi
0xffffff800042a4c2	jne		0xffffff800042a4d9

0xffffff800042a4c4	movq	0x6999b5(%rip), %rax
0xffffff800042a4cb	movq	0x488(%rax), %rdi
0xffffff800042a4d2	movq	%rdi, 0x6cebd7(%rip)

0xffffff800042a4d9	addq	$0x2, %rdi
0xffffff800042a4dd	movl	$0x2, %esi
0xffffff800042a4e2	callq	0xffffff8000402580
0xffffff800042a4e7	movzwl	%ax, %eax
0xffffff800042a4ea	cmpl	$0x1910, %eax
0xffffff800042a4ef	movl	$0x2000, %eax
0xffffff800042a4f4	movl	$0x1000, %ecx
0xffffff800042a4f9	cmovel	%eax, %ecx
0xffffff800042a4fc	movl	%ecx, _xcpm_cpu_model(%rip)
0xffffff800042a502	movl	$0x0, 0x6028e8(%rip)

This routine has no matching case number for the Ivy Bridge E, Haswell E and Broadwell E processors. That is why we lower the model number to make it match with a supported processors model. Like we are using a normal Ivy Bridge, Haswell or Broadwell processor. A simple but effective trick it seems.

I hope that my explanation about all this helps you to understand what we are doing.

Edit: Make sure that you either use a SMBIOS model/board-id with FrequencyVectors data in its plist, or patch it with help of freqVectorsEdit.sh v2.3.

You can verify that the FrequencyVector data is loaded with help of sysctl -n machdep.xcpm.vectors_loaded_count

Tips:

1.) The X86PlatformPlugin.kext will only load with the plugin-type property is set on the first logical CPU. This however is not enough to enable XCPM mode. No. You may still use AppleIntelCPUPowerManagement.kext Even when X86PlatformShim.kext is loaded.

2.) The FrequencyVectors data in the plist is used to configure power management, and is not the same for all models/board-ids. Please use one that works for your setup.

3.) If sysctl -n machdep.xcpm.vectors_loaded_count returns 0 then the FrequencyVectors data is not being used. Backup the plist for your board-id and replace it with a different plist.

4.) If you use ssdtPRGen.sh to generate your ssdt_pr.aml then make sure to use the -turbo [top-turbo-frequency] argument for overclocked setups.

5.) Check for XCPM related errors at boot time. Like this: X86PlatformShim::start – Failed to send stepper. You got to fix errors or things may not work properly.

TODOs:

1.) Fix LFM frequency (fixed to 800MHz).
2.) Figure out what MSRs trigger a reboot and only block them. Not all other supported MSRs as well.

354 thoughts on “XCPM for unsupported Processor…

  1. Hi Pike,

    Thanks for all info in you’r blog that really help me for set up my system. After long setup the power management it’s working but still missing the C3 States. And my MSR it’s still in lock. Am I need to patch bios for make this MSR unlock? And how to enable the C3 states, I’m using Asus X99 Strix and i7-6900k.
    And also I am still use FakeCpuID 0x040674 for make system running.
    Please take a look on the output of AppleIntelInfo.kext below, are theres something wrong that need to fix?

    Thanks

    AppleIntelInfo.kext v1.8c Copyright © 2012-2016 Pike R. Alpha. All rights reserved

    Settings:
    ——————————————
    logMSRs…………………………….: 1
    logIGPU…………………………….: 0
    logCStates………………………….: 1
    logIPGStyle…………………………: 1
    InitialTSC………………………….: 0xea91a5a5a16 (503 MHz)
    MWAIT C-States………………………: 8480

    Processor Brandstring………………..: Intel(R) Core(TM) i7-6900K CPU @ 3.20GHz

    Processor Signature………………… : 0x406F1
    ——————————————
    – Family…………………………. : 6
    – Stepping……………………….. : 1
    – Model………………………….. : 0x4F (79)

    Model Specific Registers (MSRs)
    ——————————————

    MSR_CORE_THREAD_COUNT…………(0x35) : 0xFFFFFF809CD8C300
    ——————————————
    – Core Count……………………… : 8
    – Thread Count……………………. : 16

    MSR_PLATFORM_INFO…………….(0xCE) : 0x20080C3BF3812000
    ——————————————
    – Maximum Non-Turbo Ratio………….. : 0x20 (3200 MHz)
    – Ratio Limit for Turbo Mode……….. : 1 (programmable)
    – TDP Limit for Turbo Mode…………. : 1 (programmable)
    – Low Power Mode Support…………… : 1 (LPM supported)
    – Number of ConfigTDP Levels……….. : 1 (additional TDP level(s) available)
    – Maximum Efficiency Ratio…………. : 12
    – Minimum Operating Ratio………….. : 8

    MSR_PMG_CST_CONFIG_CONTROL…….(0xE2) : 0x8400
    ——————————————
    – I/O MWAIT Redirection Enable……… : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
    – CFG Lock……………………….. : 1 (MSR locked until next reset)
    – C3 State Auto Demotion…………… : 0 (disabled/unsupported)
    – C1 State Auto Demotion…………… : 0 (disabled/unsupported)
    – C3 State Undemotion……………… : 0 (disabled/unsupported)
    – C1 State Undemotion……………… : 0 (disabled/unsupported)
    – Package C-State Auto Demotion…….. : 0 (disabled/unsupported)
    – Package C-State Undemotion……….. : 0 (disabled/unsupported)

    MSR_PMG_IO_CAPTURE_BASE……….(0xE4) : 0x10414
    ——————————————
    – LVL_2 Base Address………………. : 0x414
    – C-state Range…………………… : 1 (C6 is the max C-State to include)

    IA32_MPERF…………………..(0xE7) : 0x91D99D7C2
    IA32_APERF…………………..(0xE8) : 0x7E54D3A60
    MSR_0x150……………………(0x150) : 0x72525

    MSR_FLEX_RATIO……………….(0x194) : 0xE0000
    ——————————————

    MSR_IA32_PERF_STATUS………….(0x198) : 0x18C000000D00
    ——————————————
    – Current Performance State Value…… : 0xD00 (1300 MHz)

    MSR_IA32_PERF_CONTROL…………(0x199) : 0xA00
    ——————————————
    – Target performance State Value……. : 0xA00 (1000 MHz)
    – Intel Dynamic Acceleration……….. : 0 (IDA engaged)

    IA32_CLOCK_MODULATION…………(0x19A) : 0x0
    IA32_THERM_STATUS…………….(0x19C) : 0x88460000

    IA32_MISC_ENABLES…………….(0x1A0) : 0x850089
    ——————————————
    – Fast-Strings……………………. : 1 (enabled)
    – Automatic Thermal Control Circuit…. : 1 (enabled)
    – Performance Monitoring…………… : 1 (available)
    – Enhanced Intel SpeedStep Technology.. : 1 (enabled)

    MSR_TEMPERATURE_TARGET………..(0x1A2) : 0x640A00
    ——————————————
    – Turbo Attenuation Units………….. : 0
    – Temperature Target………………. : 100
    – TCC Activation Offset……………. : 0

    MSR_MISC_PWR_MGMT…………….(0x1AA) : 0x402000
    ——————————————
    – EIST Hardware Coordination……….. : 0 (enabled)

    MSR_TURBO_RATIO_LIMIT…………(0x1AD) : 0x2828282828282828
    ——————————————

    IA32_ENERGY_PERF_BIAS…………(0x1B0) : 0x0

    MSR_POWER_CTL………………..(0x1FC) : 0x29040059
    ——————————————
    – C1E Enable……………………….: 0

    MSR_RAPL_POWER_UNIT…………..(0x606) : 0xA0E03
    ——————————————
    – Power Units…………………….. : 3 (1/8 Watt)
    – Energy Status Units……………… : 14 (61 micro-Joules)
    – Time Units …………………….. : 10 (976.6 micro-Seconds)

    MSR_PKG_POWER_LIMIT…………..(0x610) : 0x7FFF80015FFF8
    ——————————————
    – Package Power Limit #1…………… : 4095 Watt
    – Enable Power Limit #1……………. : 1 (enabled)
    – Package Clamping Limitation #1……. : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
    – Time Window for Power Limit #1……. : 10 (2560 milli-Seconds)
    – Package Power Limit #2…………… : 4095 Watt
    – Enable Power Limit #2……………. : 1 (enabled)
    – Package Clamping Limitation #2……. : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
    – Time Window for Power Limit #2……. : 3 (20 milli-Seconds)
    – Lock…………………………… : 0 (MSR not locked)

    MSR_PKG_ENERGY_STATUS…………(0x611) : 0x32DFD0A
    ——————————————
    – Total Energy Consumed……………. : 3255 Joules (Watt = Joules / seconds)

    MSR_PKG_POWER_INFO……………(0x614) : 0x1780460
    ——————————————
    – Thermal Spec Power………………. : 140 Watt
    – Minimum Power…………………… : 0
    – Maximum Power…………………… : 0
    – Maximum Time Window……………… : 0

    MSR_PP0_POWER_LIMIT…………..(0x638) : 0x0

    MSR_PP0_ENERGY_STATUS…………(0x639) : 0x0

    MSR_TURBO_ACTIVATION_RATIO…….(0x64C) : 0x0

    MSR_PKGC3_IRTL……………….(0x60a) : 0x0
    MSR_PKGC6_IRTL……………….(0x60b) : 0x0
    MSR_PKG_C2_RESIDENCY………….(0x60d) : 0x0
    MSR_PKG_C3_RESIDENCY………….(0x3f8) : 0x0
    MSR_PKG_C2_RESIDENCY………….(0x60d) : 0x0
    MSR_PKG_C6_RESIDENCY………….(0x3f9) : 0x0

    IA32_TSC_DEADLINE…………….(0x6E0) : 0xEA91DE6DEC9

    CPU Ratio Info:
    ——————————————
    Base Clock Frequency (BLCK)…………. : 100 MHz
    Maximum Efficiency Ratio/Frequency…….: 12 (1200 MHz)
    Maximum non-Turbo Ratio/Frequency……..: 32 (3200 MHz)
    Maximum Turbo Ratio/Frequency…………: 40 (4000 MHz)
    P-State ratio * 100 = Frequency in MHz
    ——————————————
    CPU P-States [ (12) 22 ]
    CPU C6-Cores [ 0 2 4 6 8 10 13 15 ]
    CPU C6-Cores [ 0 2 4 6 8 10 13 14 15 ]
    CPU C6-Cores [ 0 2 4 6 8 10 12 13 14 15 ]
    CPU P-States [ (12) 22 27 ]
    CPU C6-Cores [ 0 2 4 5 6 8 10 12 13 14 15 ]
    CPU P-States [ (12) 13 22 27 ]
    CPU C6-Cores [ 0 1 2 3 4 5 6 8 10 12 13 14 15 ]
    CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 ]
    CPU P-States [ (12) 13 18 22 27 ]
    CPU P-States [ 12 13 17 18 22 27 (37) ]
    CPU P-States [ (12) 13 16 17 18 22 27 37 ]
    CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ]
    CPU P-States [ (12) 13 16 17 18 22 26 27 37 ]
    CPU P-States [ (12) 13 15 16 17 18 22 26 27 37 ]
    CPU P-States [ (12) 13 15 16 17 18 22 26 27 28 37 ]
    CPU P-States [ (12) 13 14 15 16 17 18 22 26 27 28 37 ]
    CPU P-States [ (12) 13 14 15 16 17 18 20 22 26 27 28 37 ]
    CPU P-States [ 12 13 14 15 16 17 18 20 22 24 26 27 28 (37) ]
    CPU P-States [ 12 13 14 15 16 17 18 19 20 22 24 26 27 28 (37) ]
    CPU P-States [ (12) 13 14 15 16 17 18 19 20 22 23 24 26 27 28 37 ]
    CPU P-States [ 12 13 14 15 16 17 18 19 20 22 23 24 26 27 28 37 (40) ]
    CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 (37) 40 ]
    CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 34 37 40 ]
    CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 34 37 40 ]
    CPU P-States [ 12 (13) 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 34 37 40 ]
    CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 32 34 37 40 ]
    CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 32 34 37 40 ]
    CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 37 40 ]
    CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 37 (38) 40 ]
    CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 (37) 38 40 ]
    CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 34 35 36 (37) 38 40 ]
    CPU P-States [ (12) 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 40 ]
    CPU P-States [ 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 (40) ]

  2. Hi Pike,

    I have continued my tests, and i can see the same results of a jumping CPU frequency with windows.

    When i disable EIST (only use C-States in Bios) and boot into Windows, then the CPU jumps from min. to max. multiplier.

    Read write everything shows me this msr settings

    0x01A0: 840089
    0x01AA: 400000
    0xE2: 403

    When i boot with EIST, then CPU stays at min. (12) multiplier.

    0x01A0: 850089
    0x01AA: 400000
    0xE2: 403

    The same MSR settings used with OS X give me bad CPU performance, my CPU don´t use max multiplier and can´t get full performance.

    I also have noticed, xeon shows a value in msr 0x064C. Haswell-E/Broadwell-E shows there always 0x0?

    I hope this help some specialist to investigate this problem.

  3. I can get xcpm working with using FakeCPUID 0x040652, but only using this reboot fix:

    reboot fix Sierra © Pike R. Alpha
    Find: VUiJ5UFXQVZBVUFUU1BBidZBifdIiftFhf8PhA==
    Replace: w5CJ5UFXQVZBVUFUU1BBidZBifdIiftFhf8PhA==

    If I don’t have reboot fix, the boot is just stuck on:
    OsxAptioFixDrv: Starting overrides for System\Library\CoreServices\boot.efi
    Using reloc block: yes, hibernate wake: no
    ++++++++++++++++++++++++++++++++++++++++++++++

    I have Asus X99-A patched using UEFIPatch.

    AppleIntelInfo.kext v1.8c Copyright © 2012-2016 Pike R. Alpha. All rights reserved

    Settings:
    ------------------------------------------
    logMSRs..................................: 1
    logIGPU..................................: 0
    logCStates...............................: 1
    logIPGStyle..............................: 1
    InitialTSC...............................: 0xf07f05a4c7 (31 MHz)
    MWAIT C-States...........................: 8480

    Processor Brandstring....................: Intel(R) Core(TM) i7-5820K CPU @ 3.30GHz

    Processor Signature..................... : 0x306F2
    ------------------------------------------
    - Family............................... : 6
    - Stepping............................. : 2
    - Model................................ : 0x3F (63)

    Model Specific Registers (MSRs)
    ------------------------------------------

    MSR_CORE_THREAD_COUNT............(0x35) : 0xFFFFFF803B2D9700
    ------------------------------------------
    - Core Count........................... : 6
    - Thread Count......................... : 12

    MSR_PLATFORM_INFO................(0xCE) : 0x20080C3BF3812100
    ------------------------------------------
    - Maximum Non-Turbo Ratio.............. : 0x21 (3300 MHz)
    - Ratio Limit for Turbo Mode........... : 1 (programmable)
    - TDP Limit for Turbo Mode............. : 1 (programmable)
    - Low Power Mode Support............... : 1 (LPM supported)
    - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)
    - Maximum Efficiency Ratio............. : 12
    - Minimum Operating Ratio.............. : 8

    MSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x400
    ------------------------------------------
    - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
    - CFG Lock............................. : 0 (MSR not locked)
    - C3 State Auto Demotion............... : 0 (disabled/unsupported)
    - C1 State Auto Demotion............... : 0 (disabled/unsupported)
    - C3 State Undemotion.................. : 0 (disabled/unsupported)
    - C1 State Undemotion.................. : 0 (disabled/unsupported)
    - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
    - Package C-State Undemotion........... : 0 (disabled/unsupported)

    MSR_PMG_IO_CAPTURE_BASE..........(0xE4) : 0x10414
    ------------------------------------------
    - LVL_2 Base Address................... : 0x414
    - C-state Range........................ : 1 (C6 is the max C-State to include)

    IA32_MPERF.......................(0xE7) : 0x777659587
    IA32_APERF.......................(0xE8) : 0x9D297D497

    MSR_FLEX_RATIO...................(0x194) : 0xE0000
    ------------------------------------------

    MSR_IA32_PERF_STATUS.............(0x198) : 0x295200002D00
    ------------------------------------------
    - Current Performance State Value...... : 0x2D00 (4500 MHz)

    MSR_IA32_PERF_CONTROL............(0x199) : 0xC00
    ------------------------------------------
    - Target performance State Value....... : 0xC00 (1200 MHz)
    - Intel Dynamic Acceleration........... : 0 (IDA engaged)

    IA32_CLOCK_MODULATION............(0x19A) : 0x0
    IA32_THERM_STATUS................(0x19C) : 0x88420000

    IA32_MISC_ENABLES................(0x1A0) : 0x840089
    ------------------------------------------
    - Fast-Strings......................... : 1 (enabled)
    - Automatic Thermal Control Circuit.... : 1 (enabled)
    - Performance Monitoring............... : 1 (available)
    - Enhanced Intel SpeedStep Technology.. : 0 (disabled)

    MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x670A00
    ------------------------------------------
    - Turbo Attenuation Units.............. : 0
    - Temperature Target................... : 103
    - TCC Activation Offset................ : 0

    MSR_MISC_PWR_MGMT................(0x1AA) : 0x400000
    ------------------------------------------
    - EIST Hardware Coordination........... : 0 (enabled)

    MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x22222D2D2D2D2D2D
    ------------------------------------------

    IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x0

    MSR_POWER_CTL....................(0x1FC) : 0x29040059
    ------------------------------------------
    - C1E Enable............................: 0

    MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
    ------------------------------------------
    - Power Units.......................... : 3 (1/8 Watt)
    - Energy Status Units.................. : 14 (61 micro-Joules)
    - Time Units .......................... : 10 (976.6 micro-Seconds)

    MSR_PKG_POWER_LIMIT..............(0x610) : 0x7FFF80015FFF8
    ------------------------------------------
    - Package Power Limit #1............... : 4095 Watt
    - Enable Power Limit #1................ : 1 (enabled)
    - Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
    - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)
    - Package Power Limit #2............... : 4095 Watt
    - Enable Power Limit #2................ : 1 (enabled)
    - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
    - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)
    - Lock................................. : 0 (MSR not locked)

    MSR_PKG_ENERGY_STATUS............(0x611) : 0x1E8F6FC
    ------------------------------------------
    - Total Energy Consumed................ : 1955 Joules (Watt = Joules / seconds)

    MSR_PKG_POWER_INFO...............(0x614) : 0x1280460
    ------------------------------------------
    - Thermal Spec Power................... : 140 Watt
    - Minimum Power........................ : 0
    - Maximum Power........................ : 0
    - Maximum Time Window.................. : 0

    MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

    MSR_PP0_ENERGY_STATUS............(0x639) : 0x0

    MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0

    MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x21
    MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x940000001E0460
    MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x94000000000000
    MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
    MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
    MSR_PKGC6_IRTL...................(0x60b) : 0x0
    MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x0
    MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x0

    IA32_TSC_DEADLINE................(0x6E0) : 0xF0820FFEF1

    CPU Ratio Info:
    ------------------------------------------
    Base Clock Frequency (BLCK)............. : 100 MHz
    Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
    Maximum non-Turbo Ratio/Frequency........: 33 (3300 MHz)
    Maximum Turbo Ratio/Frequency............: 45 (4500 MHz)
    P-State ratio * 100 = Frequency in MHz
    ------------------------------------------
    CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 ]
    CPU P-States [ (12) 23 26 27 28 29 30 31 32 34 35 36 37 38 39 40 41 42 43 44 45 ]

    Any recommendations? The system seems to be stable, just want to make sure everything is set up properly.

  4. Guys, I’m getting the same “Clover hw.busfrequency error detected”… what’s the exact syntax to fix the QPI in clover config.plist ? Would really appreciate it..

  5. I seem to have the same bouncing frequency issue as others have reported. Tested in Windows, and the system idles nicely around 800Mhz and ramps up to 4Ghz as needed.

    I noticed I also have the warning about the bus speed incorrect in Clover and applied the fix, my output is below. Interestingly, my C/P states are very much minimized with this QPI fix in place. Without it, I have a nice dump of states at the end of the kext output.

    I posted earlier about this, but I also suffer from loss of throttling after a sleep.wake cycle, with the cpu peaking at a constant 4Ghz.

    Any observations appreciated.

    AppleIntelInfo.kext v1.8 Copyright © 2012-2016 Pike R. Alpha. All rights reserved

    Settings:
    ------------------------------------------
    logMSRs..................................: 1
    logIGPU..................................: 0
    logCStates...............................: 1
    logIPGStyle..............................: 1
    InitialTSC...............................: 0x15985c3944 (2 MHz)
    MWAIT C-States...........................: 8480

    Processor Brandstring....................: Intel(R) Core(TM) i7-5820K CPU @ 3.30GHz

    Processor Signature..................... : 0x306F2
    ------------------------------------------
    - Family............................... : 6
    - Stepping............................. : 2
    - Model................................ : 0x3F (63)

    Model Specific Registers (MSRs)
    ------------------------------------------

    MSR_CORE_THREAD_COUNT............(0x35) : 0x6000C
    ------------------------------------------
    - Core Count........................... : 6
    - Thread Count......................... : 12

    MSR_PLATFORM_INFO................(0xCE) : 0x80C3BF3812100
    ------------------------------------------
    - Maximum Non-Turbo Ratio.............. : 0x21 (3300 MHz)
    - Ratio Limit for Turbo Mode........... : 1 (programmable)
    - TDP Limit for Turbo Mode............. : 1 (programmable)
    - Low Power Mode Support............... : 1 (LPM supported)
    - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)
    - Maximum Efficiency Ratio............. : 12
    - Minimum Operating Ratio.............. : 8

    MSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x403
    ------------------------------------------
    - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
    - CFG Lock............................. : 0 (MSR not locked)
    - C3 State Auto Demotion............... : 0 (disabled/unsupported)
    - C1 State Auto Demotion............... : 0 (disabled/unsupported)
    - C3 State Undemotion.................. : 0 (disabled/unsupported)
    - C1 State Undemotion.................. : 0 (disabled/unsupported)
    - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
    - Package C-State Undemotion........... : 0 (disabled/unsupported)

    MSR_PMG_IO_CAPTURE_BASE..........(0xE4) : 0x10414
    ------------------------------------------
    - LVL_2 Base Address................... : 0x414
    - C-state Range........................ : 1 (C6 is the max C-State to include)

    IA32_MPERF.......................(0xE7) : 0x13CBACAEE
    IA32_APERF.......................(0xE8) : 0x14E07E042

    MSR_FLEX_RATIO...................(0x194) : 0xE0000
    ------------------------------------------

    MSR_IA32_PERF_STATUS.............(0x198) : 0x266200002800
    ------------------------------------------
    - Current Performance State Value...... : 0x2800 (4000 MHz)

    MSR_IA32_PERF_CONTROL............(0x199) : 0xFF00
    ------------------------------------------
    - Target performance State Value....... : 0xFF00 (25500 MHz)
    - Intel Dynamic Acceleration........... : 0 (IDA engaged)

    IA32_CLOCK_MODULATION............(0x19A) : 0x0
    IA32_THERM_STATUS................(0x19C) : 0x883D0000

    IA32_MISC_ENABLES................(0x1A0) : 0x850089
    ------------------------------------------
    - Fast-Strings......................... : 1 (enabled)
    - Automatic Thermal Control Circuit.... : 1 (enabled)
    - Performance Monitoring............... : 1 (available)
    - Enhanced Intel SpeedStep Technology.. : 1 (enabled)

    MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x5E0A00
    ------------------------------------------
    - Turbo Attenuation Units.............. : 0
    - Temperature Target................... : 94
    - TCC Activation Offset................ : 0

    MSR_MISC_PWR_MGMT................(0x1AA) : 0x400000
    ------------------------------------------
    - EIST Hardware Coordination........... : 0 (enabled)

    MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x2222282828282828
    ------------------------------------------
    - Maximum Ratio Limit for C01.......... : 28 (4000 MHz)
    - Maximum Ratio Limit for C02.......... : 28 (4000 MHz)
    - Maximum Ratio Limit for C03.......... : 28 (4000 MHz)
    - Maximum Ratio Limit for C04.......... : 28 (4000 MHz)
    - Maximum Ratio Limit for C05.......... : 28 (4000 MHz)
    - Maximum Ratio Limit for C06.......... : 28 (4000 MHz)

    IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x1
    ------------------------------------------
    - Power Policy Preference...............: 1 (highest performance)

    MSR_POWER_CTL....................(0x1FC) : 0x2104005B
    ------------------------------------------
    - C1E Enable............................: 1

    MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
    ------------------------------------------
    - Power Units.......................... : 3 (1/8 Watt)
    - Energy Status Units.................. : 14 (61 micro-Joules)
    - Time Units .......................... : 10 (976.6 micro-Seconds)

    MSR_PKG_POWER_LIMIT..............(0x610) : 0x7FFD00014EA82
    ------------------------------------------
    - Package Power Limit #1............... : 3408 Watt
    - Enable Power Limit #1................ : 1 (enabled)
    - Package Clamping Limitation #1....... : 0 (disabled)
    - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)
    - Package Power Limit #2............... : 4090 Watt
    - Enable Power Limit #2................ : 1 (enabled)
    - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
    - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)
    - Lock................................. : 0 (MSR not locked)

    MSR_PKG_ENERGY_STATUS............(0x611) : 0x67D158
    ------------------------------------------
    - Total Energy Consumed................ : 415 Joules (Watt = Joules / seconds)

    MSR_PKG_POWER_INFO...............(0x614) : 0x1280460
    ------------------------------------------
    - Thermal Spec Power................... : 140 Watt
    - Minimum Power........................ : 0
    - Maximum Power........................ : 0
    - Maximum Time Window.................. : 0

    MSR_PP0_POWER_LIMIT..............(0x638) : 0x14FFD0
    ------------------------------------------
    - Power Limit.......................... : 4090 Watt
    - Enable Power Limit................... : 1 (enabled)
    - Clamping Limitation.................. : 0 (disabled)
    - Time Window for Power Limit.......... : 10 (10240 milli-Seconds)
    - Lock................................. : 0 (MSR not locked)

    MSR_PP0_ENERGY_STATUS............(0x639) : 0x0

    MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0

    MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x21
    MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x940000001E0460
    MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x94000000000000
    MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
    MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
    MSR_PKGC6_IRTL...................(0x60b) : 0x0
    MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x0
    MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x0

    IA32_TSC_DEADLINE................(0x6E0) : 0x159AABAB18

    CPU Ratio Info:
    ------------------------------------------
    Base Clock Frequency (BLCK)............. : 100 MHz
    Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
    Maximum non-Turbo Ratio/Frequency........: 33 (3300 MHz)
    Maximum Turbo Ratio/Frequency............: 40 (4000 MHz)
    P-State ratio * 100 = Frequency in MHz
    ------------------------------------------
    CPU P-States [ 37 (40) ]
    CPU C6-Cores [ 2 4 6 8 10 ]
    CPU C6-Cores [ 2 4 6 8 9 10 11 ]

  6. Hi Piker…i know my reply is typical by a newbie but please check my AppleIntelInfo log…something is not working correctly in my system (x99 deluxe U3.1 msr unlocked + 5960X) running sierra final

    AppleIntelInfo.kext v1.8c Copyright © 2012-2016 Pike R. Alpha. All rights reserved

    Settings:
    ------------------------------------------
    logMSRs..................................: 1
    logIGPU..................................: 0
    logCStates...............................: 1
    logIPGStyle..............................: 1
    InitialTSC...............................: 0x10f99e7de1a (38 MHz)
    MWAIT C-States...........................: 8480

    Processor Brandstring....................: Intel(R) Core(TM) i7-5960X CPU @ 3.00GHz

    Processor Signature..................... : 0x306F2
    ------------------------------------------
    - Family............................... : 6
    - Stepping............................. : 2
    - Model................................ : 0x3F (63)

    Model Specific Registers (MSRs)
    ------------------------------------------

    MSR_CORE_THREAD_COUNT............(0x35) : 0x0
    ------------------------------------------
    - Core Count........................... : 8
    - Thread Count......................... : 16

    MSR_PLATFORM_INFO................(0xCE) : 0x20080C3BF3811E00
    ------------------------------------------
    - Maximum Non-Turbo Ratio.............. : 0x1E (3000 MHz)
    - Ratio Limit for Turbo Mode........... : 1 (programmable)
    - TDP Limit for Turbo Mode............. : 1 (programmable)
    - Low Power Mode Support............... : 1 (LPM supported)
    - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)
    - Maximum Efficiency Ratio............. : 12
    - Minimum Operating Ratio.............. : 8

    MSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x400
    ------------------------------------------
    - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
    - CFG Lock............................. : 0 (MSR not locked)
    - C3 State Auto Demotion............... : 0 (disabled/unsupported)
    - C1 State Auto Demotion............... : 0 (disabled/unsupported)
    - C3 State Undemotion.................. : 0 (disabled/unsupported)
    - C1 State Undemotion.................. : 0 (disabled/unsupported)
    - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
    - Package C-State Undemotion........... : 0 (disabled/unsupported)

    MSR_PMG_IO_CAPTURE_BASE..........(0xE4) : 0x10414
    ------------------------------------------
    - LVL_2 Base Address................... : 0x414
    - C-state Range........................ : 1 (C6 is the max C-State to include)

    IA32_MPERF.......................(0xE7) : 0x2A5A6D18C8
    IA32_APERF.......................(0xE8) : 0x30BE11A19A

    MSR_FLEX_RATIO...................(0x194) : 0xE0000
    ------------------------------------------

    MSR_IA32_PERF_STATUS.............(0x198) : 0x271C00002800
    ------------------------------------------
    - Current Performance State Value...... : 0x2800 (4000 MHz)

    MSR_IA32_PERF_CONTROL............(0x199) : 0xFF00
    ------------------------------------------
    - Target performance State Value....... : 0xFF00 (25500 MHz)
    - Intel Dynamic Acceleration........... : 0 (IDA engaged)

    IA32_CLOCK_MODULATION............(0x19A) : 0x0
    IA32_THERM_STATUS................(0x19C) : 0x884E0000

    IA32_MISC_ENABLES................(0x1A0) : 0x840089
    ------------------------------------------
    - Fast-Strings......................... : 1 (enabled)
    - Automatic Thermal Control Circuit.... : 1 (enabled)
    - Performance Monitoring............... : 1 (available)
    - Enhanced Intel SpeedStep Technology.. : 0 (disabled)

    MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x691200
    ------------------------------------------
    - Turbo Attenuation Units.............. : 0
    - Temperature Target................... : 105
    - TCC Activation Offset................ : 0

    MSR_MISC_PWR_MGMT................(0x1AA) : 0x400000
    ------------------------------------------
    - EIST Hardware Coordination........... : 0 (enabled)

    MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x2828282828282828
    ------------------------------------------

    IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x0

    MSR_POWER_CTL....................(0x1FC) : 0x2904005B
    ------------------------------------------
    - C1E Enable............................: 1

    MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
    ------------------------------------------
    - Power Units.......................... : 3 (1/8 Watt)
    - Energy Status Units.................. : 14 (61 micro-Joules)
    - Time Units .......................... : 10 (976.6 micro-Seconds)

    MSR_PKG_POWER_LIMIT..............(0x610) : 0x7FFF80015FFF8
    ------------------------------------------
    - Package Power Limit #1............... : 4095 Watt
    - Enable Power Limit #1................ : 1 (enabled)
    - Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
    - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)
    - Package Power Limit #2............... : 4095 Watt
    - Enable Power Limit #2................ : 1 (enabled)
    - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
    - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)
    - Lock................................. : 0 (MSR not locked)

    MSR_PKG_ENERGY_STATUS............(0x611) : 0x1F2EE3
    ------------------------------------------
    - Total Energy Consumed................ : 124 Joules (Watt = Joules / seconds)

    MSR_PKG_POWER_INFO...............(0x614) : 0x1280460
    ------------------------------------------
    - Thermal Spec Power................... : 140 Watt
    - Minimum Power........................ : 0
    - Maximum Power........................ : 0
    - Maximum Time Window.................. : 0

    MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

    MSR_PP0_ENERGY_STATUS............(0x639) : 0x0

    MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0

    MSR_CONFIG_TDP_NOMINAL...........(0x648) : 0x1E
    MSR_CONFIG_TDP_LEVEL1............(0x649) : 0x940000001B0460
    MSR_CONFIG_TDP_LEVEL2............(0x64a) : 0x94000000000000
    MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
    MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x0
    MSR_PKGC6_IRTL...................(0x60b) : 0x0
    MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x0
    MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x0

    IA32_TSC_DEADLINE................(0x6E0) : 0x10FA83D6090

    CPU Ratio Info:
    ------------------------------------------
    Base Clock Frequency (BLCK)............. : 100 MHz
    Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
    Maximum non-Turbo Ratio/Frequency........: 30 (3000 MHz)
    Maximum Turbo Ratio/Frequency............: 40 (4000 MHz)
    P-State ratio * 100 = Frequency in MHz
    ------------------------------------------
    CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ]
    CPU P-States [ 12 18 19 20 21 22 23 24 25 27 28 29 30 31 32 35 36 37 38 (40) ]

      • Of course i noticed that there is something wrong in package limit but i don’t know how to solve. My bios settings are in Auto, just a moderate overclock to 4000…

      • Thanks for your answer. I will try to set a real value after reading more about different bios settings. I will let you know.

      • Hi pike
        XCPM worked well Gigabyte X99 Gaming G1
        Thank you.

        Last login: Sun Oct 9 00:51:54 on ttys000
        manoranjans-Pro:~ manoranjan$ sudo chown -R root:wheel /Users/manoranjan/Desktop/AppleIntelInfo.kext
        Password:
        manoranjans-Pro:~ manoranjan$ sudo chmod -R 755 /Users/manoranjan/Desktop/AppleIntelInfo.kext
        manoranjans-Pro:~ manoranjan$ sudo kextload /Users/manoranjan/Desktop/AppleIntelInfo.kext
        manoranjans-Pro:~ manoranjan$ sudo cat /tmp/AppleIntelInfo.dat

        AppleIntelInfo.kext v1.8e Copyright © 2012-2016 Pike R. Alpha. All rights reserved

        Settings:

  7. How do I find the location of 0x01A0 in different kernels so that I can do this myself after updates instead of needing someone else to provide me with patch info?

    Thanks!

  8. Sorry, another question. This method works perfectly with any Haswell-EP CPUs with a CPUID of 0x0306f2.
    http://www.insanelymac.com/forum/topic/315579-el-capitan-xcpm-for-x99-one-patch-solution/

    However, Xeon Haswell-E’s have a CPUID of 0x0306f1. What would I need to change to allow me to use that same method of achieving XCPM?

    I tried FakeCPUID in Clover, but that did not change the reported CPUID in AppleIntelInfo, nor did XCPM behavior change.

    Thanks!

    • Are you talking about the ‘turbo-drop’ problem (won’t run flat out all the time) or the ‘frequency-bounching’ problem (drops down to the minimum frequency and then back up)?

      If that is a yes, then I would start by comparing the output of AppleIntelInfo.kext of both processors because there might be something that we are missing.

      p.s. The Haswell-E and the Xeon processor both report 0x3F as model so that should be fine.

  9. Hi Pike, On insanelymac forum, thanks to your work, people open many thread with different solution to have xcpm working in a best way.
    If it possible could you “the Finder” make some clearance?
    Your reboot fix patch method for sierra linked to fakecpuid 40764 and Brumbaer 5960x patch allows user with Broadwell E/EP cpu to have access at a partial XCPM.Common problem is no lower steps in appleintleinfo output, no c3 residency, no c3 states
    in my case I have a stable system (Xeon broadwell EP 2696 V4)

    Now in the last day other xcpm solution based from your finding in this thread is on air!
    setting this Patches with clover:
    find
    qgEAANwzAAAAAAAAAAAAAAAAAAAAAAAAAQ==
    replace
    qgEAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA==

    find
    oAEAANwzAAAAAAAAAAAAAAAAAABAAAAAAQAF
    replace
    oAEAANwzAAAAAAAAAAAAAAAAAABAAAAAAQAE

    find
    OgYAANwzAAAAAAAAAAAAAB8AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
    replace OgYAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA
    find
    QgYAANwzAAAAAAAAAAAAAB8AAAAAAAAAGA==
    replace
    QgYAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA==

    find
    4gAAAEwAAAAAAAAAAAAAAA8EAAAAAAAABQAAHg==
    replace
    4gAAAEwAAAAAAAAAAAAAAA8EAAAAAAAABwAAfg==

    produce an output with C3, a programmed msr 0xE2 =7E000007

    this:
    MSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x7E000007
    ------------------------------------------
    - I/O MWAIT Redirection Enable......... : 0 (not enabled)
    - CFG Lock............................. : 0 (MSR not locked)
    - C3 State Auto Demotion............... : 1 (enabled)
    - C1 State Auto Demotion............... : 1 (enabled)
    - C3 State Undemotion.................. : 1 (enabled)
    - C1 State Undemotion.................. : 1 (enabled)
    - Package C-State Auto Demotion........ : 1 (enabled)
    - Package C-State Undemotion........... : 1 (enabled)

    and this:
    MSR_CONFIG_TDP_CONTROL...........(0x64b) : 0x0
    MSR_TURBO_ACTIVATION_RATIO.......(0x64c) : 0x2E
    MSR_PKGC6_IRTL...................(0x60b) : 0x0
    MSR_PKG_C2_RESIDENCY.............(0x60d) : 0xAF73BC5368F
    MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x3CE141
    MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0xB21573FDB7A

    IA32_TSC_DEADLINE................(0x6E0) : 0x30D4F0BC715A

    In my case I have also C3 cores fro 0 to 43
    P states Always without lower steps from 13 to 18
    same temperature and so on

    What do you think about this 5 Patches?
    It seems to have the same behaviour of reboot fix patch, but Output of AppleIntelInfo seems to be more complete

    Thank you for your time

    • Fabio,

      I do not believe in a “partial XCPM” as you say. To me it (XCPM) either works or not. The fact that it may react differently, than what you expect, is another matter. It may as well be very simple, by wiping the Package Clamping Limitation #1/#2 i.e. bits 16 and 48 of MSR(0x610). You can do that by compiling AppleIntelInfo.kext yourself with a small addition on line 1250:
      UInt64 msr_value = rdmsr64(MSR_PKG_POWER_LIMIT);
      // Setting bits.
      // msr_value |= (1L << 16);
      // msr_value |= (1L << 48);
      // Clearing bits.
      msr_value &= ~(1L << 16);
      msr_value &= ~(1L << 48);
      wrmsr64(MSR_PKG_POWER_LIMIT, msr_value);

      I have also included ways to sets bits.

      • Hi Pike Thank you for your help
        I have the same your idea for XCPM (works or not)
        But maybe X99 Platform has some strange behaviour
        With EIST disabled also in windows there are frequency jumping
        Bur With EIST enabled windows have a correct behaviour and no loss of performance
        follow my result with adding line you suggested:

        AppleIntelInfo.kext v1.8e Copyright © 2012-2016 Pike R. Alpha. All rights reserved

        Settings:
        ------------------------------------------
        logMSRs..................................: 1
        logIGPU..................................: 0
        logCStates...............................: 1
        logIPGStyle..............................: 1
        InitialTSC...............................: 0x3da2c2e3378 (192 MHz)
        MWAIT C-States...........................: 8480

        Processor Brandstring....................: Intel(R) Xeon(R) CPU E5-2696 v4 @ 2.20GHz

        Processor Signature..................... : 0x406F1
        ------------------------------------------
        - Family............................... : 6
        - Stepping............................. : 1
        - Model................................ : 0x4F (79)

        Model Specific Registers (MSRs)
        ------------------------------------------

        MSR_CORE_THREAD_COUNT............(0x35) : 0x0
        ------------------------------------------
        - Core Count........................... : 22
        - Thread Count......................... : 44

        MSR_PLATFORM_INFO................(0xCE) : 0x20080C3BF2811600
        ------------------------------------------
        - Maximum Non-Turbo Ratio.............. : 0x16 (2200 MHz)
        - Ratio Limit for Turbo Mode........... : 1 (programmable)
        - TDP Limit for Turbo Mode............. : 1 (programmable)
        - Low Power Mode Support............... : 1 (LPM supported)
        - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)
        - Maximum Efficiency Ratio............. : 12
        - Minimum Operating Ratio.............. : 8

        MSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x7E000007
        ------------------------------------------
        - I/O MWAIT Redirection Enable......... : 0 (not enabled)
        - CFG Lock............................. : 0 (MSR not locked)
        - C3 State Auto Demotion............... : 1 (enabled)
        - C1 State Auto Demotion............... : 1 (enabled)
        - C3 State Undemotion.................. : 1 (enabled)
        - C1 State Undemotion.................. : 1 (enabled)
        - Package C-State Auto Demotion........ : 1 (enabled)
        - Package C-State Undemotion........... : 1 (enabled)

        MSR_PMG_IO_CAPTURE_BASE..........(0xE4) : 0x10414
        ------------------------------------------
        - LVL_2 Base Address................... : 0x414
        - C-state Range........................ : 1 (C-States not included, I/O MWAIT redirection not enabled)

        IA32_MPERF.......................(0xE7) : 0x4A5D07FE00
        IA32_APERF.......................(0xE8) : 0x5DC28AAA97
        MSR_0x150........................(0x150) : 0x1F00000000

        MSR_FLEX_RATIO...................(0x194) : 0x0
        ------------------------------------------

        MSR_IA32_PERF_STATUS.............(0x198) : 0x18ED00000C00
        ------------------------------------------
        - Current Performance State Value...... : 0xC00 (1200 MHz)

        MSR_IA32_PERF_CONTROL............(0x199) : 0x2500
        ------------------------------------------
        - Target performance State Value....... : 0x2500 (3700 MHz)
        - Intel Dynamic Acceleration........... : 0 (IDA engaged)

        IA32_CLOCK_MODULATION............(0x19A) : 0x0
        IA32_THERM_STATUS................(0x19C) : 0x88500000

        IA32_MISC_ENABLES................(0x1A0) : 0x840089
        ------------------------------------------
        - Fast-Strings......................... : 1 (enabled)
        - Automatic Thermal Control Circuit.... : 1 (enabled)
        - Performance Monitoring............... : 1 (available)
        - Processor Event Based Sampling....... : 0 (PEBS supported)
        - Enhanced Intel SpeedStep Technology.. : 0 (disabled)
        - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
        - CFG Lock............................. : 0 (MSR not locked)

        MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x640200
        ------------------------------------------
        - Turbo Attenuation Units.............. : 0
        - Temperature Target................... : 100
        - TCC Activation Offset................ : 0

        MSR_MISC_PWR_MGMT................(0x1AA) : 0x402000
        ------------------------------------------
        - EIST Hardware Coordination........... : 0 (hardware coordination enabled)
        - Energy/Performance Bias support...... : 1
        - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
        - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

        MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x1E1F202122232525
        ------------------------------------------
        - Maximum Ratio Limit for C01.......... : 25 (3700 MHz)
        - Maximum Ratio Limit for C02.......... : 25 (3700 MHz)
        - Maximum Ratio Limit for C03.......... : 23 (3500 MHz)
        - Maximum Ratio Limit for C04.......... : 22 (3400 MHz)
        - Maximum Ratio Limit for C05.......... : 21 (3300 MHz)
        - Maximum Ratio Limit for C06.......... : 20 (3200 MHz)
        - Maximum Ratio Limit for C07.......... : 1F (3100 MHz)
        - Maximum Ratio Limit for C08.......... : 1E (3000 MHz)

        MSR_TURBO_RATIO_LIMIT1...........(0x1AE) : 0x1C1C1C1C1C1C1C1D
        ------------------------------------------
        - Maximum Ratio Limit for C09.......... : 1D (2900 MHz)
        - Maximum Ratio Limit for C10.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C11.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C12.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C13.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C14.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C15.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C16.......... : 1C (2800 MHz)

        MSR_TURBO_RATIO_LIMIT2...........(0x1AF) : 0x1C1C1C1C1C1C1C1C
        ------------------------------------------
        - Maximum Ratio Limit for C17.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C18.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C19.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C20.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C21.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C22.......... : 1C (2800 MHz)

        IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x1
        ------------------------------------------
        - Power Policy Preference...............: 1 (highest performance)

        MSR_POWER_CTL....................(0x1FC) : 0x2904005B
        ------------------------------------------
        - C1E Enable............................: 1 (enabled)

        MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
        ------------------------------------------
        - Power Units.......................... : 3 (1/8 Watt)
        - Energy Status Units.................. : 14 (61 micro-Joules)
        - Time Units .......................... : 10 (976.6 micro-Seconds)

        MSR_PKG_POWER_LIMIT..............(0x610) : 0x685A0001484B0
        ------------------------------------------
        - Package Power Limit #1............... : 150 Watt
        - Enable Power Limit #1................ : 1 (enabled)
        - Package Clamping Limitation #1....... : 0 (disabled)
        - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)
        - Package Power Limit #2............... : 180 Watt
        - Enable Power Limit #2................ : 1 (enabled)
        - Package Clamping Limitation #2....... : 0 (disabled)
        - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)
        - Lock................................. : 0 (MSR not locked)

        MSR_PKG_ENERGY_STATUS............(0x611) : 0xC9D50B
        ------------------------------------------
        - Total Energy Consumed................ : 807 Joules (Watt = Joules / seconds)

        MSR_PKG_POWER_INFO...............(0x614) : 0x2F0A18028804B0
        ------------------------------------------
        - Thermal Spec Power................... : 150 Watt
        - Minimum Power........................ : 0
        - Maximum Power........................ : 323
        - Maximum Time Window.................. : 0

        MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

        MSR_PP0_ENERGY_STATUS............(0x639) : 0x0

        MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0

        MSR_PKGC3_IRTL...................(0x60a) : 0x0
        MSR_PKGC6_IRTL...................(0x60b) : 0x0
        MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x2364231F60
        MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x227406
        MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0xB3C9160754

        IA32_TSC_DEADLINE................(0x6E0) : 0x3DA39A6118C

        CPU Ratio Info:
        ------------------------------------------
        Base Clock Frequency (BLCK)............. : 100 MHz
        Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
        Maximum non-Turbo Ratio/Frequency........: 22 (2200 MHz)
        Maximum Turbo Ratio/Frequency............: 37 (3700 MHz)
        P-State ratio * 100 = Frequency in MHz
        ------------------------------------------
        CPU P-States [ 28 35 (37) ]
        CPU C3-Cores [ 0 1 2 6 8 11 15 16 22 26 30 ]
        CPU C6-Cores [ 0 1 3 4 6 9 11 12 14 17 18 20 23 24 27 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ (12) 27 28 35 37 ]
        CPU C3-Cores [ 0 1 2 3 5 6 7 8 10 11 15 16 22 26 30 ]
        CPU C6-Cores [ 0 1 2 3 4 6 7 8 9 11 12 13 14 15 17 18 20 21 23 24 25 27 29 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 10 11 14 15 16 22 26 30 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 20 21 22 23 24 25 27 29 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ (12) 26 27 28 35 37 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 27 29 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ (12) 26 27 28 29 35 37 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 27 28 29 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ (12) 26 27 28 29 30 35 37 ]
        CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 10 11 14 15 16 22 26 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ (12) 26 27 28 29 30 34 35 37 ]
        CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 22 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU C3-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 14 15 16 17 22 23 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ (12) 26 27 28 29 30 32 34 35 37 ]

      • Fabio,

        Now that you can set/clear bits it is just a matter of time before someone finds out what the problem is. That is, if the values of certain MSR’s are the problem.

      • Pike, surely Knowledge will save us! Or it destroy us (more pessimistic vision) 🙂
        till that moment, is there a chance to disable EIST if it is enabled in bios?
        It seems that there was this possibility but I loose the bit to patch..If I don’t remeber well you talk in your blog about this.

  10. I think it’s a problem with the programming msr 0x199 and reading 0x198?

    When EIST is enabled and msr 199 is active used, CPU use lower P-States, but won’t stay at max multiplier under load. Performance is not stable, sometimes CPU uses max. multiplier, then it drops immediatelly down to min. under full load.

    Without active msr 199 (EIST) disabled, we have max. performance, but CPU don’t use lower states + umping frequency in idle.

    There Must be a problem, and we don’t find/see. All CPUs with more than 4 cores have this problems when xcpm is active.

    Disabling msr 0x199 with a Kernel patch (edited the msr to 00 00 in the sub routine) and enabling EIST shows the same result. Full performance, but no lower p states. Msr 0x199 is not programmed.

    I have no idea, and i don’t understand assembler code, but there is a msr199.kext where someone tried to find a solution. But no success, problems are not solved.

    So should we take a closer look to this subroutines?

    • If it drops down to a lower frequency, then that is probably for a good reason. I think that the first thing you and others should do is figure out what that condition is. AppleIntelInfo.kext may provide the information that you are looking for (see MSR_CORE_PERF_LIMIT_REASONS/0x64F).

    • Hi pike
      Thanks for XCPM supported.
      When you have time please check my report.
      Thank you.
      Last login: Mon Oct 31 03:07:47 on console
      manoranjans-Pro:~ manoranjan$ sudo chown -R root:wheel /Users/manoranjan/Desktop/AppleIntelInfo.kext
      Password:
      manoranjans-Pro:~ manoranjan$ sudo chmod -R 755 /Users/manoranjan/Desktop/AppleIntelInfo.kext
      manoranjans-Pro:~ manoranjan$ sudo kextload /Users/manoranjan/Desktop/AppleIntelInfo.kext
      manoranjans-Pro:~ manoranjan$ sudo cat /tmp/AppleIntelInfo.dat

      AppleIntelInfo.kext v1.8e Copyright © 2012-2016 Pike R. Alpha. All rights reserved

      Settings:

  11. Hi Pike, how are you?

    Mind if I tap into your wisdom for a bit? From what I can see there is a hard limit set in xnu for the amount of cores OS can use (seems like its set for 64 now), is there a way to bump that limit or it’s more integrated then just in kernel?

    • I am fine. Thanks.

      About your question. Never been that fortunate, to have so many cores, but from what I remember it checks for 0x3f somewhere in the kernel. In _ml_init_max_cpus? Sorry. Can’t remember it. You may want to change it to a higher/lower value and give it a go.

      • Thank you for you feedback.

        I’ve wasted good part of the day trying to figure out how, what and where.
        Any hints on how to do that and convert that string to a something that Clover understands?

        One more favor, I’ve been struggling with some odd issues on the already installed system, the terminal crashes all the time, weirdly seems like I’m the only one with that problem.

        Crashed Thread: 0 Dispatch queue: com.apple.main-thread

        Exception Type: EXC_BAD_ACCESS (SIGSEGV)
        Exception Codes: KERN_INVALID_ADDRESS at 0x0000000000000010
        Exception Note: EXC_CORPSE_NOTIFY

        Termination Signal: Segmentation fault: 11
        Termination Reason: Namespace SIGNAL, Code 0xb
        Terminating Process: exc handler [0]

        VM Regions Near 0x10:
        –>
        __TEXT 0000000105cbf000-0000000105d86000 [ 796K] r-x/rwx SM=COW /Applications/Utilities/Terminal.app/Contents/MacOS/Terminal

        Full report:
        http://pastebin.com/raw/JHNNuEbr

        The only patch I’m using is CPUID patch.

        Thank a lot,

      • 1.) otool -tVj /S*/L*/Kernels/kernel > kernel-disassembled.txt
        2.) open kernel-disassembled.txt
        3.) Search for: “_ml_init_max_cpus:”
        4.) Look for: “cmp rcx, 0x3f”

        Tip: You can convert the hex byte code with help of:
        echo -n '488d4fff4883f93f7712'|xxd -r -p|base64

        5.) Replace the 3f with anything that you want.

        About the terminal.app issue. Try to open the Terminal.app from another volume. If that works then either re-install or replace the Terminal.app

      • Sorry Pike, I must sound like a broken records… I’m just learning 🙂

        I found this:

        ffffff8000403e16 48 83 f9 3f cmpq $0x3f, %rcx

        Its a bit different, but I’m trying to figure out which any of those number are what and how do you change them?

      • You are looking for the “3f” there i.e. 63 decimal. You take three lines of hex byte code and convert it like in my example. The one you showed here with “48 83 f9 3f” would be the second line. Don’t forget to remove the spaces.

      • Pike regarding this subject, could be related also a line present in AppleACPIPlatform.kext (cpu init) to try to bypass cpu limit (seems 64 cores/threads in Sierra)
        Do you think it is possible?

        Thank you

      • Hi Pike,
        I confirm there is the same instruction cmp rcx, 0x3f , just one time in all AppleACPIPlatform.kext, even its patched the same as kernel, still crashing at boot

  12. Hi Pike,

    thank you for helping us! This ist great.

    Only for information, this is the location where i startet some changing of bits….

    sub_ffffff800041f1c0:

    this sub_ffffff800041f1c0 is called from _xcpm_dvfs_start, from _xcpm_dvfs_configure,

    and also called from: sub_ffffff800041e850 ; _xcpm_cpu_control+1590

    _xcpm_cpu_control+1590 is called from sub_ffffff800041fc60 ; XREF=_xcpm_timer+1253, _xcpm_urgency+4778, sub_ffffff8000422680+422
    or from _xcpm_cpu_control
    or from sub_ffffff8000428f30 ; XREF=_xcpm_cpu_control+1769

    really confusing to me 🙂

    So I disabled msr 199 here:

    ffffff800041f252 mov eax, ebx ; XREF=sub_ffffff800041f1c0+37
    ffffff800041f254 shl eax, 0x8
    ffffff800041f257 mov ecx, 0x199
    ffffff800041f25c xor edx, edx

    i used this HEX kernel patch: Find: 89D8C1E008B99901 Replace 89D8C1E008B90000, or 89D8C1E008B9C300

    So, msr 0x199 was disabled. xcpm don´t write to it.

    And with EIST enabled (msr 0x1A0:850089), the cpu uses max. multiplier of 35.
    To solve this, i write manually to msr 0x199, set it to E2, and cpu uses max. multi. x46.

    Then the Performace is perfect, same as disabling EIST (msr 0x1A0: 840089) and our old patches. But without EIST, CPU jumps at idle. We know this.

    Then i tested some stupid things 🙂

    I patched bits at this location:

    ffffff800041f254 shl eax, 0x8

    For fun: find: 89D8C1E008B99901 replace:89D8C1E00AB99901

    i got better performance, CPU reaches faster x46, but it does this not permanent, it also goes down to a lower multiplier when running Geekbench. But the time to reach a higher multiplier is now shorter.
    The idle frequency is now not so „smooth“ (with EIST and without patches, i got a flat line at x12).

    I know, stupid to change this, but i tested again with a value of 89D8C1E004B99901.

    With this, performance is really bad 🙂 it only uses x12.

    I think msr 0x199 is very important, for full performance and for ar flat line at idle.

    It´s really frustrating, but there is nothing at apples open source
    /xnu/xnu-3789.21.1/osfmk/x86_64/xcpm was never published.

  13. Hi Pike,

    i read out msr 0x199 / x0198 in idle, and when Geekbench is running.
    Test with EIST enabled!

    And msr 0x199 don´t change!

    MSR 0x198 shows only 3 states! (Jumping frequency, we already know, is here again???)

    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 198 returns value 0x2300
    RDMSR 198 returns value 0x2300
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2300
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0xc00
    RDMSR 198 returns value 0x2300
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0xc00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0xc00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2300
    RDMSR 198 returns value 0xc00
    RDMSR 198 returns value 0x2e00
    RDMSR 199 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0x2e00
    RDMSR 198 returns value 0xc00
    RDMSR 198 returns value 0x2300
    RDMSR 198 returns value 0x2e00

    This is unexpected, the should chnage????

    Running Windows with EIST, this 2 msrs permanently show different states.

    I think, xcpm don´t work correct.

    We got only P-States working, and some C-States, controlled by Bios/CPU?

  14. Hi Piker – I hope I am not dragging this off-topic and if so then I apologise as I am having a mad theory session again.

    If Apple is migrating away from AICPM and going purely for Kernel based power management, could it be that Apple could be thinking of adopting different processors such as the soon to be released AMD Zen family.

    If that is the case and if I understand the Zen cpu’s ability to do data encryption directly on the chip would this spell the end of the hackintosh ?

    • I can’t speak for Apple, but I personally hope that they stick to Intel processors. XCPM is working mighty fine for me with all processors thus far, including the Broadwell-E’s, so I wouldn’t mind.

      About the end of hackintosh. Well. Apple’s new filesystem will technically eliminate legacy boot loaders, and who know what the future will bring. We’ll have to wait and see…

  15. @balamut
    ffffff8000403e164883f93f kernel value (3f means 63
    ffffff8000403e164883f957 patch 57means 83

    should be
    find
    ////gABAPhZIg/k/
    repalace
    ////gABAPhZIg/lX
    you have to verify by yourself if i did in the right way

    • Hi, I did it with patching in your way with 59 for 87 cores ( my rig, 2×22 cores). Was able to boot without hyperthreading, 44 cores, so the patch doesn’t break something in the kernel ( EC10.11.6), but with the hyperthreading activated, got the same KP as usual with acpiplatform kext.
      I also tried with only 16 activated cores per CPU and HT activated ( 64 cores), but only 32 were recognized by the OS, the os does’nt care about hyperthreading. So even it’s possible to break cpu limit, that need other stuffs to be useful.

      • Hi Philippe
        Which motherboard do you use?
        For now I have a single 2696v4 cpu with a single cpu slot motherboard
        I did for the sake of testing a patch lowering 64 value to 32 in mac Os sierra kernel ..in my head I would like to force osx to use only 32 for cores/threads instead my real 44
        With this patch system does not start..
        So maybe it is not the right place to search a solution in my opinion

      • Hi Fabio, using X10DAX slightly overcocked motherboard with ElCapitan 10.11.6. ( If I find a way to boot Maveriks instead with GTX980 suppurt, It will be 100 times better for me.
        To limit cores, that’s a Bios setting. Why do you want to lower value by patch ? I tryed you patch, able to boot withe 44 physical cores activated, but it doesn’t change anything If I activate hyperthreading : still crashing at boot

      • Hi Philippe
        I don’t know if we are off topic here maybe we can discuss on that forum link if you want
        I see different strange data in your output
        Our cpu has a maximal turbo for 2 cores of x 37 (3700) . I don’t see it from your output
        Then, in full load you should have a frequency of x28 (2800) for all your cores/threads
        i.e. when you use cinebench 15 cpu bench or geek bench during some LLVM tests
        you can monitoring these parameters using IPG (Intel power gadget app)
        If in your bios you have EIST parameter try to disable it
        if I have it enabled I have to use solution 3 with oarksit modified patch to have max performances in higher turbo levels

    • Hi Fabio, I uses X10DAX, a slightly overclocked mobo and running on it 10.11.6 with 44 physical cores.
      To limit number of cores, first disable hyperthreading in Bios. But why do you want to limit them ?

      • Hi Philippe
        I have tried to see if it was the right place to “hack” without applying any change in bios parameters, but that bit does not override bios parameters.
        I have not a dual CPU system
        It is curious that you see exactly 44 cores an not 64 cores as that bit limit (3f) could suggest
        In that condition (patch without hyperthreading) is your system stable?
        How do you know if it uses 22 cores per cpu or all 44 cores/thread of one of it?
        thank you

      • That’s not curious ; the system just see what the bios send to him ; in my case, 44 physical cores, the bios is set to disable hyperthreading, so no more cores wil be detected by the os. As I wrote, I tryed to get this number of 64 cores enabled, 32 physical and 32 from Hyperthreading, setting in bios 32 cores activated and hyperthreading activated, I got il the system only 32 cores recognized, like cores provided by hyperthreading weren’t recognized ; but if I boot the computer with all cores and hyperthreading activated (88) I get Kernel panic.
        So remaining 2 questions :
        -why hyperthreading is recognised by acpiplatform kext ( this one that causing KP because of the number of core limit to enable is break
        -what other thing we have to patch in Kernel to remove this limit of 64 core ?
        May be Pike could have an idea ?

      • Hi Fabio,
        I didn’t try yet, I’m travelling for 2 days. May b be the patch with this option could unlock the trouble…

      • Maybe Philippe,
        It is useful if you have a dual system with windows/linux and OS X.
        In this way also if OS X is not working with all cores/threads set in bios you can leave bios with Hyperthreading enabled and with cpus=44 you can force OS X to start ..maybe! 🙂

      • Hi Fabio, I’m back.
        Tryed with the -cpus=88 but stlil kp whith acpiplatform kext…. May something else hav to be patched in kernel…

      • Hi Fabio. I tried cpu=88, still KP. Enabling just 32 core with cpu=64, I got hyperthreading working. For the full 88 cores we have to find something else.
        Hi Pikeralpha, what do you think about all this ?

      • Digging on kernel I see many cpu thread count parameters..maybe Pike could help to try the right one…but maybe it is only impossible to hack! 🙂

      • Stable and working, but nvidia driver refuses to load ( I have gtx 980 in my system). with 44 cores, nvidia drives loads. I did’t succeed to have it booting without nullcpupowermanagement.kext. I tryed to generate ssdt table, but with custom ssdt, it crashes after 10 minutes and still needs nullcpupowermanagement.kext.
        to be able to boot.

      • El capitan has a different kernel so you have to modify them
        But with correct el capitan patches it is working
        I prefer solution with pikeralpha reboot fix

        But all are working well and rig is stable at all

      • Hi Fabio,
        following your link and post, with some 10.11.6 Pikeralpha’s patches, custom ssdt generated byPikeralpha’s script, I got this :

        AppleIntelInfo.kext v2.0 Copyright © 2012-2016 Pike R. Alpha. All rights reserved
        enableHWP…………………………..: 0

        Settings:
        ——————————————
        logMSRs…………………………….: 1
        logIGPU…………………………….: 0
        logCStates………………………….: 1
        logIPGStyle…………………………: 1
        InitialTSC………………………….: 0xc49299927a (35 MHz)
        MWAIT C-States………………………: 8480

        Processor Brandstring………………..:

        Processor Signature………………… : 0x406F1
        ——————————————
        – Family…………………………. : 6
        – Stepping……………………….. : 1
        – Model………………………….. : 0x4F (79)

        Model Specific Registers (MSRs)
        ——————————————

        MSR_CORE_THREAD_COUNT…………(0x35) : 0x0
        ——————————————
        – Core Count……………………… : 22
        – Thread Count……………………. : 22

        MSR_PLATFORM_INFO…………….(0xCE) : 0x20080C3BFB811800
        ——————————————
        – Maximum Non-Turbo Ratio………….. : 0x18 (2400 MHz)
        – Ratio Limit for Turbo Mode……….. : 1 (programmable)
        – TDP Limit for Turbo Mode…………. : 1 (programmable)
        – Low Power Mode Support…………… : 1 (LPM supported)
        – Number of ConfigTDP Levels……….. : 1 (additional TDP level(s) available)
        – Maximum Efficiency Ratio…………. : 12
        – Minimum Operating Ratio………….. : 8

        MSR_PMG_CST_CONFIG_CONTROL…….(0xE2) : 0x8403
        ——————————————
        – I/O MWAIT Redirection Enable……… : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
        – CFG Lock……………………….. : 1 (MSR locked until next reset)
        – C3 State Auto Demotion…………… : 0 (disabled/unsupported)
        – C1 State Auto Demotion…………… : 0 (disabled/unsupported)
        – C3 State Undemotion……………… : 0 (disabled/unsupported)
        – C1 State Undemotion……………… : 0 (disabled/unsupported)
        – Package C-State Auto Demotion…….. : 0 (disabled/unsupported)
        – Package C-State Undemotion……….. : 0 (disabled/unsupported)

        MSR_PMG_IO_CAPTURE_BASE……….(0xE4) : 0x10414
        ——————————————
        – LVL_2 Base Address………………. : 0x414
        – C-state Range…………………… : 1 (C6 is the max C-State to include)

        IA32_MPERF…………………..(0xE7) : 0x5F4678D840
        IA32_APERF…………………..(0xE8) : 0x215D23E60A
        MSR_0x150……………………(0x150) : 0x0

        MSR_FLEX_RATIO……………….(0x194) : 0x0
        ——————————————

        MSR_IA32_PERF_STATUS………….(0x198) : 0x209A00001E00
        ——————————————
        – Current Performance State Value…… : 0x1E00 (3000 MHz)

        MSR_IA32_PERF_CONTROL…………(0x199) : 0x2500
        ——————————————
        – Target performance State Value……. : 0x2500 (3700 MHz)
        – Intel Dynamic Acceleration……….. : 0 (IDA engaged)

        IA32_CLOCK_MODULATION…………(0x19A) : 0x0

        IA32_THERM_INTERRUPT………….(0x19B) : 0x0

        IA32_THERM_STATUS…………….(0x19C) : 0x882C0000
        ——————————————
        – Thermal Status………………….. : 0
        – Thermal Log…………………….. : 0
        – PROCHOT # or FORCEPR# event………. : 0
        – PROCHOT # or FORCEPR# log………… : 0
        – Critical Temperature Status………. : 0
        – Critical Temperature log…………. : 0
        – Thermal Threshold #1 Status………. : 0
        – Thermal Threshold #1 log…………. : 0
        – Thermal Threshold #2 Status………. : 0
        – Thermal Threshold #2 log…………. : 0
        – Power Limitation Status………….. : 0
        – Power Limitation log…………….. : 0
        – Current Limit Status…………….. : 0
        – Current Limit log……………….. : 0
        – Cross Domain Limit Status………… : 0
        – Cross Domain Limit log…………… : 0
        – Digital Readout…………………. : 44
        – Resolution in Degrees Celsius…….. : 1
        – Reading Valid…………………… : 1 (valid)

        MSR_THERM2_CTL……………….(0x19D) : 0x0

        IA32_MISC_ENABLES…………….(0x1A0) : 0x850089
        ——————————————
        – Fast-Strings……………………. : 1 (enabled)
        – FOPCODE compatibility mode Enable…. : 0
        – Automatic Thermal Control Circuit…. : 1 (enabled)
        – Split-lock Disable………………. : 0
        – Performance Monitoring…………… : 1 (available)
        – Bus Lock On Cache Line Splits Disable : 0
        – Hardware prefetch Disable………… : 0
        – Processor Event Based Sampling……. : 0 (PEBS supported)
        – GV1/2 legacy Enable……………… : 0
        – Enhanced Intel SpeedStep Technology.. : 1 (enabled)
        – MONITOR FSM…………………….. : 1 (MONITOR/MWAIT supported)
        – Adjacent sector prefetch Disable….. : 0
        – CFG Lock……………………….. : 0 (MSR not locked)
        – xTPR Message Disable…………….. : 1 (disabled)

        MSR_TEMPERATURE_TARGET………..(0x1A2) : 0x4E0A00
        ——————————————
        – Turbo Attenuation Units………….. : 0
        – Temperature Target………………. : 78
        – TCC Activation Offset……………. : 0

        MSR_MISC_PWR_MGMT…………….(0x1AA) : 0x402000
        ——————————————
        – EIST Hardware Coordination……….. : 0 (hardware coordination enabled)
        – Energy/Performance Bias support…… : 1
        – Energy/Performance Bias………….. : 0 (disabled/MSR not visible to software)
        – Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

        MSR_TURBO_RATIO_LIMIT…………(0x1AD) : 0x1C1D1E1F20212323
        ——————————————
        – Maximum Ratio Limit for C01………. : 23 (3500 MHz)
        – Maximum Ratio Limit for C02………. : 23 (3500 MHz)
        – Maximum Ratio Limit for C03………. : 21 (3300 MHz)
        – Maximum Ratio Limit for C04………. : 20 (3200 MHz)
        – Maximum Ratio Limit for C05………. : 1F (3100 MHz)
        – Maximum Ratio Limit for C06………. : 1E (3000 MHz)
        – Maximum Ratio Limit for C07………. : 1D (2900 MHz)
        – Maximum Ratio Limit for C08………. : 1C (2800 MHz)

        MSR_TURBO_RATIO_LIMIT1………..(0x1AE) : 0x1C1C1C1C1C1C1C1C
        ——————————————
        – Maximum Ratio Limit for C09………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C10………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C11………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C12………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C13………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C14………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C15………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C16………. : 1C (2800 MHz)

        MSR_TURBO_RATIO_LIMIT2………..(0x1AF) : 0x1C1C1C1C1C1C1C1C
        ——————————————
        – Maximum Ratio Limit for C17………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C18………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C19………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C20………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C21………. : 1C (2800 MHz)
        – Maximum Ratio Limit for C22………. : 1C (2800 MHz)

        IA32_ENERGY_PERF_BIAS…………(0x1B0) : 0x0

        MSR_POWER_CTL………………..(0x1FC) : 0x2904005B
        ——————————————
        – Bi-Directional Processor Hot……….: 1 (enabled)
        – C1E Enable……………………….: 1 (enabled)

        MSR_RAPL_POWER_UNIT…………..(0x606) : 0xA0E03
        ——————————————
        – Power Units…………………….. : 3 (1/8 Watt)
        – Energy Status Units……………… : 14 (61 micro-Joules)
        – Time Units …………………….. : 10 (976.6 micro-Seconds)

        MSR_PKG_POWER_LIMIT…………..(0x610) : 0x785A0001584B0
        ——————————————
        – Package Power Limit #1…………… : 150 Watt
        – Enable Power Limit #1……………. : 1 (enabled)
        – Package Clamping Limitation #1……. : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
        – Time Window for Power Limit #1……. : 10 (2560 milli-Seconds)
        – Package Power Limit #2…………… : 180 Watt
        – Enable Power Limit #2……………. : 1 (enabled)
        – Package Clamping Limitation #2……. : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
        – Time Window for Power Limit #2……. : 3 (20 milli-Seconds)
        – Lock…………………………… : 0 (MSR not locked)

        MSR_PKG_ENERGY_STATUS…………(0x611) : 0x118C91D0
        ——————————————
        – Total Energy Consumed……………. : 17970 Joules (Watt = Joules / seconds)

        MSR_PKG_POWER_INFO……………(0x614) : 0x2F0A18034804B0
        ——————————————
        – Thermal Spec Power………………. : 150 Watt
        – Minimum Power…………………… : 0
        – Maximum Power…………………… : 323
        – Maximum Time Window……………… : 0

        MSR_PP0_POWER_LIMIT…………..(0x638) : 0x0

        MSR_PP0_ENERGY_STATUS…………(0x639) : 0x0

        MSR_TURBO_ACTIVATION_RATIO…….(0x64C) : 0x0

        MSR_PKGC3_IRTL……………….(0x60a) : 0x0
        MSR_PKGC6_IRTL……………….(0x60b) : 0x0
        MSR_PKG_C2_RESIDENCY………….(0x60d) : 0x1AFD50F208
        MSR_PKG_C3_RESIDENCY………….(0x3f8) : 0x0
        MSR_PKG_C6_RESIDENCY………….(0x3f9) : 0x8184A7F58

        IA32_TSC_DEADLINE…………….(0x6E0) : 0xC4A5B40B5E

        CPU Ratio Info:
        ——————————————
        Base Clock Frequency (BLCK)…………. : 100 MHz
        Maximum Efficiency Ratio/Frequency…….: 12 (1200 MHz)
        Maximum non-Turbo Ratio/Frequency……..: 24 (2400 MHz)
        Maximum Turbo Ratio/Frequency…………: 35 (3500 MHz)
        P-State ratio * 100 = Frequency in MHz
        ——————————————
        CPU P-States [ 27 (28) 33 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 ]
        CPU P-States [ 26 27 28 (32) 33 ]
        CPU P-States [ 26 27 28 32 33 (35) ]
        CPU P-States [ 26 27 28 32 33 (34) 35 ]
        CPU P-States [ 26 27 28 (30) 32 33 34 35 ]
        CPU P-States [ 26 27 28 (29) 30 32 33 34 35 ]
        CPU P-States [ 26 27 28 29 30 31 (32) 33 34 35 ]
        CPU P-States [ (12) 26 27 28 29 30 31 32 33 34 35 ]
        CPU P-States [ 12 20 26 27 28 29 30 31 32 33 34 (35) ]
        CPU P-States [ (12) 20 25 26 27 28 29 30 31 32 33 34 35 ]
        CPU P-States [ 12 20 24 25 26 27 28 29 30 31 32 33 34 (35) ]
        CPU P-States [ 12 20 23 24 25 26 27 28 29 30 31 32 33 34 (35) ]
        CPU P-States [ (12) 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 ]

        But dispute of the fact I use your patch to get max turbo at 2700 Mhz, I succeed just one time to get max turbo at 2700 Mhz instead of 2500 Mhz, and stil not able to reproduce one more time

      • edit (add my Appleintelinfo output:


        fabios-Mac-Pro:desktop fabio$ sudo cat /tmp/AppleIntelInfo.dat

        AppleIntelInfo.kext v2.0 Copyright © 2012-2016 Pike R. Alpha. All rights reserved
        enableHWP................................: 0

        Settings:
        ------------------------------------------
        logMSRs..................................: 1
        logIGPU..................................: 0
        logCStates...............................: 1
        logIPGStyle..............................: 1
        InitialTSC...............................: 0x1edb64ca384 (96 MHz)
        MWAIT C-States...........................: 8480

        Processor Brandstring....................: Intel(R) Xeon(R) CPU E5-2696 v4 @ 2.20GHz

        Processor Signature..................... : 0x406F1
        ------------------------------------------
        - Family............................... : 6
        - Stepping............................. : 1
        - Model................................ : 0x4F (79)

        Model Specific Registers (MSRs)
        ------------------------------------------

        MSR_CORE_THREAD_COUNT............(0x35) : 0xFFFFFF8110015500
        ------------------------------------------
        - Core Count........................... : 22
        - Thread Count......................... : 44

        MSR_PLATFORM_INFO................(0xCE) : 0x20080C3BF2811600
        ------------------------------------------
        - Maximum Non-Turbo Ratio.............. : 0x16 (2200 MHz)
        - Ratio Limit for Turbo Mode........... : 1 (programmable)
        - TDP Limit for Turbo Mode............. : 1 (programmable)
        - Low Power Mode Support............... : 1 (LPM supported)
        - Number of ConfigTDP Levels........... : 1 (additional TDP level(s) available)
        - Maximum Efficiency Ratio............. : 12
        - Minimum Operating Ratio.............. : 8

        MSR_PMG_CST_CONFIG_CONTROL.......(0xE2) : 0x402
        ------------------------------------------
        - I/O MWAIT Redirection Enable......... : 1 (enabled, IO read of MSR(0xE4) mapped to MWAIT)
        - CFG Lock............................. : 0 (MSR not locked)
        - C3 State Auto Demotion............... : 0 (disabled/unsupported)
        - C1 State Auto Demotion............... : 0 (disabled/unsupported)
        - C3 State Undemotion.................. : 0 (disabled/unsupported)
        - C1 State Undemotion.................. : 0 (disabled/unsupported)
        - Package C-State Auto Demotion........ : 0 (disabled/unsupported)
        - Package C-State Undemotion........... : 0 (disabled/unsupported)

        MSR_PMG_IO_CAPTURE_BASE..........(0xE4) : 0x10414
        ------------------------------------------
        - LVL_2 Base Address................... : 0x414
        - C-state Range........................ : 1 (C6 is the max C-State to include)

        IA32_MPERF.......................(0xE7) : 0x4A31EB8AAF
        IA32_APERF.......................(0xE8) : 0x4B3351B581
        MSR_0x150........................(0x150) : 0x1F00000000

        MSR_FLEX_RATIO...................(0x194) : 0x0
        ------------------------------------------

        MSR_IA32_PERF_STATUS.............(0x198) : 0x263B00002500
        ------------------------------------------
        - Current Performance State Value...... : 0x2500 (3700 MHz)

        MSR_IA32_PERF_CONTROL............(0x199) : 0x2500
        ------------------------------------------
        - Target performance State Value....... : 0x2500 (3700 MHz)
        - Intel Dynamic Acceleration........... : 0 (IDA engaged)

        IA32_CLOCK_MODULATION............(0x19A) : 0x0

        IA32_THERM_INTERRUPT.............(0x19B) : 0x0

        IA32_THERM_STATUS................(0x19C) : 0x88500000
        ------------------------------------------
        - Thermal Status....................... : 0
        - Thermal Log.......................... : 0
        - PROCHOT # or FORCEPR# event.......... : 0
        - PROCHOT # or FORCEPR# log............ : 0
        - Critical Temperature Status.......... : 0
        - Critical Temperature log............. : 0
        - Thermal Threshold #1 Status.......... : 0
        - Thermal Threshold #1 log............. : 0
        - Thermal Threshold #2 Status.......... : 0
        - Thermal Threshold #2 log............. : 0
        - Power Limitation Status.............. : 0
        - Power Limitation log................. : 0
        - Current Limit Status................. : 0
        - Current Limit log.................... : 0
        - Cross Domain Limit Status............ : 0
        - Cross Domain Limit log............... : 0
        - Digital Readout...................... : 80
        - Resolution in Degrees Celsius........ : 1
        - Reading Valid........................ : 1 (valid)

        MSR_THERM2_CTL...................(0x19D) : 0x0

        IA32_MISC_ENABLES................(0x1A0) : 0x850089
        ------------------------------------------
        - Fast-Strings......................... : 1 (enabled)
        - FOPCODE compatibility mode Enable.... : 0
        - Automatic Thermal Control Circuit.... : 1 (enabled)
        - Split-lock Disable................... : 0
        - Performance Monitoring............... : 1 (available)
        - Bus Lock On Cache Line Splits Disable : 0
        - Hardware prefetch Disable............ : 0
        - Processor Event Based Sampling....... : 0 (PEBS supported)
        - GV1/2 legacy Enable.................. : 0
        - Enhanced Intel SpeedStep Technology.. : 1 (enabled)
        - MONITOR FSM.......................... : 1 (MONITOR/MWAIT supported)
        - Adjacent sector prefetch Disable..... : 0
        - CFG Lock............................. : 0 (MSR not locked)
        - xTPR Message Disable................. : 1 (disabled)

        MSR_TEMPERATURE_TARGET...........(0x1A2) : 0x640200
        ------------------------------------------
        - Turbo Attenuation Units.............. : 0
        - Temperature Target................... : 100
        - TCC Activation Offset................ : 0

        MSR_MISC_PWR_MGMT................(0x1AA) : 0x402000
        ------------------------------------------
        - EIST Hardware Coordination........... : 0 (hardware coordination enabled)
        - Energy/Performance Bias support...... : 1
        - Energy/Performance Bias.............. : 0 (disabled/MSR not visible to software)
        - Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

        MSR_TURBO_RATIO_LIMIT............(0x1AD) : 0x1E1F202122232525
        ------------------------------------------
        - Maximum Ratio Limit for C01.......... : 25 (3700 MHz)
        - Maximum Ratio Limit for C02.......... : 25 (3700 MHz)
        - Maximum Ratio Limit for C03.......... : 23 (3500 MHz)
        - Maximum Ratio Limit for C04.......... : 22 (3400 MHz)
        - Maximum Ratio Limit for C05.......... : 21 (3300 MHz)
        - Maximum Ratio Limit for C06.......... : 20 (3200 MHz)
        - Maximum Ratio Limit for C07.......... : 1F (3100 MHz)
        - Maximum Ratio Limit for C08.......... : 1E (3000 MHz)

        MSR_TURBO_RATIO_LIMIT1...........(0x1AE) : 0x1C1C1C1C1C1C1C1D
        ------------------------------------------
        - Maximum Ratio Limit for C09.......... : 1D (2900 MHz)
        - Maximum Ratio Limit for C10.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C11.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C12.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C13.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C14.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C15.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C16.......... : 1C (2800 MHz)

        MSR_TURBO_RATIO_LIMIT2...........(0x1AF) : 0x1C1C1C1C1C1C1C1C
        ------------------------------------------
        - Maximum Ratio Limit for C17.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C18.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C19.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C20.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C21.......... : 1C (2800 MHz)
        - Maximum Ratio Limit for C22.......... : 1C (2800 MHz)

        IA32_ENERGY_PERF_BIAS............(0x1B0) : 0x0

        MSR_POWER_CTL....................(0x1FC) : 0x2904005B
        ------------------------------------------
        - Bi-Directional Processor Hot..........: 1 (enabled)
        - C1E Enable............................: 1 (enabled)

        MSR_RAPL_POWER_UNIT..............(0x606) : 0xA0E03
        ------------------------------------------
        - Power Units.......................... : 3 (1/8 Watt)
        - Energy Status Units.................. : 14 (61 micro-Joules)
        - Time Units .......................... : 10 (976.6 micro-Seconds)

        MSR_PKG_POWER_LIMIT..............(0x610) : 0x785A0001584B0
        ------------------------------------------
        - Package Power Limit #1............... : 150 Watt
        - Enable Power Limit #1................ : 1 (enabled)
        - Package Clamping Limitation #1....... : 1 (allow going below OS-requested P/T state during Time Window for Power Limit #1)
        - Time Window for Power Limit #1....... : 10 (2560 milli-Seconds)
        - Package Power Limit #2............... : 180 Watt
        - Enable Power Limit #2................ : 1 (enabled)
        - Package Clamping Limitation #2....... : 1 (allow going below OS-requested P/T state setting Time Window for Power Limit #2)
        - Time Window for Power Limit #2....... : 3 (20 milli-Seconds)
        - Lock................................. : 0 (MSR not locked)

        MSR_PKG_ENERGY_STATUS............(0x611) : 0x10D7F3D
        ------------------------------------------
        - Total Energy Consumed................ : 1077 Joules (Watt = Joules / seconds)

        MSR_PKG_POWER_INFO...............(0x614) : 0x2F0A18028804B0
        ------------------------------------------
        - Thermal Spec Power................... : 150 Watt
        - Minimum Power........................ : 0
        - Maximum Power........................ : 323
        - Maximum Time Window.................. : 0

        MSR_PP0_POWER_LIMIT..............(0x638) : 0x0

        MSR_PP0_ENERGY_STATUS............(0x639) : 0x0

        MSR_TURBO_ACTIVATION_RATIO.......(0x64C) : 0x0

        MSR_PKGC3_IRTL...................(0x60a) : 0x0
        MSR_PKGC6_IRTL...................(0x60b) : 0x0
        MSR_PKG_C2_RESIDENCY.............(0x60d) : 0x6CCADF4CFA
        MSR_PKG_C3_RESIDENCY.............(0x3f8) : 0x0
        MSR_PKG_C6_RESIDENCY.............(0x3f9) : 0x102441FF6AE

        IA32_TSC_DEADLINE................(0x6E0) : 0x1EDC720BDBD

        CPU Ratio Info:
        ------------------------------------------
        Base Clock Frequency (BLCK)............. : 100 MHz
        Maximum Efficiency Ratio/Frequency.......: 12 (1200 MHz)
        Maximum non-Turbo Ratio/Frequency........: 22 (2200 MHz)
        Maximum Turbo Ratio/Frequency............: 37 (3700 MHz)
        P-State ratio * 100 = Frequency in MHz
        ------------------------------------------
        CPU P-States [ 22 35 (37) ]
        CPU C6-Cores [ 1 2 4 5 6 7 8 10 11 12 14 17 19 21 24 26 29 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ 22 26 35 (37) ]
        CPU C6-Cores [ 0 1 2 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ 22 25 26 (35) 37 ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ 22 25 26 30 35 (37) ]
        CPU C6-Cores [ 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 ]
        CPU P-States [ 22 25 26 29 30 (34) 35 37 ]
        CPU P-States [ 22 25 26 28 29 30 34 35 (37) ]
        CPU P-States [ (12) 22 25 26 28 29 30 32 34 35 37 ]
        CPU P-States [ 12 22 24 25 26 28 29 30 32 34 35 (37) ]
        CPU P-States [ 12 22 24 25 26 27 28 29 30 32 34 35 (37) ]
        CPU P-States [ (12) 22 23 24 25 26 27 28 29 30 32 34 35 37 ]
        CPU P-States [ 12 21 22 23 24 25 26 27 28 29 30 32 34 35 (37) ]
        CPU P-States [ 12 21 22 23 24 25 26 27 28 29 30 32 33 34 (35) 37 ]
        CPU P-States [ 12 19 21 (22) 23 24 25 26 27 28 29 30 32 33 34 35 37 ]
        CPU P-States [ (12) 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 37 ]
        CPU P-States [ (12) 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 ]
        CPU P-States [ (12) 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 ]
        fabios-Mac-Pro:desktop fabio$

        you can see many cpu c6 e P states

  16. Hi, Pike.
    Instead of using these patches you mentioned at https://pikeralpha.wordpress.com/2016/07/26/xcpm-for-unsupported-processor/comment-page-1/#comment-6301 , you can also use ret(urn) at kernel location 0x2283a0 (Darwin 16.0.0, 10.12.0, 16A323). And confirmed, this worked for me, here is the diff:

    @@ -409785,7 +409785,7 @@
    ffffff8000428392 5d popq %rbp
    ffffff8000428393 e9 08 00 00 00 jmp 0xffffff80004283a0
    ffffff8000428398 0f 1f 84 00 00 00 00 00 nopl (%rax,%rax)
    -ffffff80004283a0 55 pushq %rbp
    +ffffff80004283a0 c3 retq
    ffffff80004283a1 48 89 e5 movq %rsp, %rbp
    ffffff80004283a4 41 57 pushq %r15
    ffffff80004283a6 41 56 pushq %r14

    Okay. This is made based on your comment, and I saw all verbs you NOP called ffffff80004283a0, so I used ret(urn) for this and works well 🙂

  17. Hi Pike,
    I’ve enabled XCPM successfully by following your idea. Thanks. But some questions I’d like to ask…
    Details:
    CPU: Intel Xeon E3 1230 V2
    SMBios: MacPro5,1 + MacBookPro 11,5 FrequencyVectors (Use ssdtPRGen.sh to inject LFM = 1200MHz and set “plugin-type” = 1 to load X86*, use freqVectorsEdit.sh to inject MacBookPro 11,5 FrequencyVectors.)
    But… I can’t get any P-States lower than x16, here is the output of AppleIntelInfo.kext:

    AppleIntelInfo.kext v2.0 Copyright © 2012-2016 Pike R. Alpha. All rights reserved
    enableHWP…………………………..: 0

    Settings:
    ——————————————
    logMSRs…………………………….: 1
    logIGPU…………………………….: 0
    logCStates………………………….: 1
    logIPGStyle…………………………: 1
    InitialTSC………………………….: 0x1923645735c9 (837 MHz)
    MWAIT C-States………………………: 4384

    Processor Brandstring………………..: Intel(R) Xeon(R) CPU E3-1230 V2 @ 3.30GHz

    Processor Signature………………… : 0x306A9
    ——————————————
    – Family…………………………. : 6
    – Stepping……………………….. : 9
    – Model………………………….. : 0x3A (58)

    Model Specific Registers (MSRs)
    ——————————————

    MSR_CORE_THREAD_COUNT…………(0x35) : 0x0
    ——————————————
    – Core Count……………………… : 4
    – Thread Count……………………. : 8

    MSR_PLATFORM_INFO…………….(0xCE) : 0x81010E0012100
    ——————————————
    – Maximum Non-Turbo Ratio………….. : 0x21 (3300 MHz)
    – Ratio Limit for Turbo Mode……….. : 0 (not programmable)
    – TDP Limit for Turbo Mode…………. : 1 (programmable)
    – Low Power Mode Support…………… : 0 (LMP not supported)
    – Number of ConfigTDP Levels……….. : 0 (only base TDP level available)
    – Maximum Efficiency Ratio…………. : 16
    – Minimum Operating Ratio………….. : 8

    MSR_PMG_CST_CONFIG_CONTROL…….(0xE2) : 0x1E000005
    ——————————————
    – I/O MWAIT Redirection Enable……… : 0 (not enabled)
    – CFG Lock……………………….. : 0 (MSR not locked)
    – C3 State Auto Demotion…………… : 1 (enabled)
    – C1 State Auto Demotion…………… : 1 (enabled)
    – C3 State Undemotion……………… : 1 (enabled)
    – C1 State Undemotion……………… : 1 (enabled)
    – Package C-State Auto Demotion…….. : 0 (disabled/unsupported)
    – Package C-State Undemotion……….. : 0 (disabled/unsupported)

    MSR_PMG_IO_CAPTURE_BASE……….(0xE4) : 0x10414
    ——————————————
    – LVL_2 Base Address………………. : 0x414
    – C-state Range…………………… : 1 (C-States not included, I/O MWAIT redirection not enabled)

    IA32_MPERF…………………..(0xE7) : 0x3F6EB20777
    IA32_APERF…………………..(0xE8) : 0x303AC8CBA5

    MSR_FLEX_RATIO……………….(0x194) : 0x0
    ——————————————

    MSR_IA32_PERF_STATUS………….(0x198) : 0x1E6C00001100
    ——————————————
    – Current Performance State Value…… : 0x1100 (1700 MHz)

    MSR_IA32_PERF_CONTROL…………(0x199) : 0x2500
    ——————————————
    – Target performance State Value……. : 0x2500 (3700 MHz)
    – Intel Dynamic Acceleration……….. : 0 (IDA engaged)

    IA32_CLOCK_MODULATION…………(0x19A) : 0x0

    IA32_THERM_INTERRUPT………….(0x19B) : 0x10
    ——————————————
    – High-Temperature Interrupt Enable…. : 0 (disabled)
    – Low-Temperature Interrupt Enable….. : 0 (disabled)
    – PROCHOT# Interrupt Enable………… : 0 (disabled)
    – FORCEPR# Interrupt Enable………… : 0 (disabled)
    – Critical Temperature Interrupt Enable : 1 (enabled)
    – Threshold #1 Value………………. : 0
    – Threshold #1 Interrupt Enable…….. : 0 (disabled)
    – Threshold #2 Value………………. : 0
    – Threshold #2 Interrupt Enable…….. : 0 (disabled)
    – Power Limit Notification Enable…… : 0 (disabled)

    IA32_THERM_STATUS…………….(0x19C) : 0x88400000
    ——————————————
    – Thermal Status………………….. : 0
    – Thermal Log…………………….. : 0
    – PROCHOT # or FORCEPR# event………. : 0
    – PROCHOT # or FORCEPR# log………… : 0
    – Critical Temperature Status………. : 0
    – Critical Temperature log…………. : 0
    – Thermal Threshold #1 Status………. : 0
    – Thermal Threshold #1 log…………. : 0
    – Thermal Threshold #2 Status………. : 0
    – Thermal Threshold #2 log…………. : 0
    – Power Limitation Status………….. : 0
    – Power Limitation log…………….. : 0
    – Current Limit Status…………….. : 0
    – Current Limit log……………….. : 0
    – Cross Domain Limit Status………… : 0
    – Cross Domain Limit log…………… : 0
    – Digital Readout…………………. : 64
    – Resolution in Degrees Celsius…….. : 1
    – Reading Valid…………………… : 1 (valid)

    MSR_THERM2_CTL……………….(0x19D) : 0x0

    IA32_MISC_ENABLES…………….(0x1A0) : 0x850089
    ——————————————
    – Fast-Strings……………………. : 1 (enabled)
    – FOPCODE compatibility mode Enable…. : 0
    – Automatic Thermal Control Circuit…. : 1 (enabled)
    – Split-lock Disable………………. : 0
    – Performance Monitoring…………… : 1 (available)
    – Bus Lock On Cache Line Splits Disable : 0
    – Hardware prefetch Disable………… : 0
    – Processor Event Based Sampling……. : 0 (PEBS supported)
    – GV1/2 legacy Enable……………… : 0
    – Enhanced Intel SpeedStep Technology.. : 1 (enabled)
    – MONITOR FSM…………………….. : 1 (MONITOR/MWAIT supported)
    – Adjacent sector prefetch Disable….. : 0
    – CFG Lock……………………….. : 0 (MSR not locked)
    – xTPR Message Disable…………….. : 1 (disabled)

    MSR_TEMPERATURE_TARGET………..(0x1A2) : 0x691400
    ——————————————
    – Turbo Attenuation Units………….. : 0
    – Temperature Target………………. : 105
    – TCC Activation Offset……………. : 0

    MSR_MISC_PWR_MGMT…………….(0x1AA) : 0x400000
    ——————————————
    – EIST Hardware Coordination……….. : 0 (hardware coordination enabled)
    – Energy/Performance Bias support…… : 1
    – Energy/Performance Bias………….. : 0 (disabled/MSR not visible to software)
    – Thermal Interrupt Coordination Enable : 1 (thermal interrupt routed to all cores)

    MSR_TURBO_RATIO_LIMIT…………(0x1AD) : 0x23242525
    ——————————————
    – Maximum Ratio Limit for C01………. : 25 (3700 MHz)
    – Maximum Ratio Limit for C02………. : 25 (3700 MHz)
    – Maximum Ratio Limit for C03………. : 24 (3600 MHz)
    – Maximum Ratio Limit for C04………. : 23 (3500 MHz)

    IA32_ENERGY_PERF_BIAS…………(0x1B0) : 0x5
    ——————————————
    – Power Policy Preference……………: 5 (balanced performance and energy saving)

    MSR_POWER_CTL………………..(0x1FC) : 0x14005F
    ——————————————
    – Bi-Directional Processor Hot……….: 1 (enabled)
    – C1E Enable……………………….: 1 (enabled)

    MSR_RAPL_POWER_UNIT…………..(0x606) : 0xA1003
    ——————————————
    – Power Units…………………….. : 3 (1/8 Watt)
    – Energy Status Units……………… : 16 (15.3 micro-Joules)
    – Time Units …………………….. : 10 (976.6 micro-Seconds)

    MSR_PKG_POWER_LIMIT…………..(0x610) : 0x1AA580001A9F40
    ——————————————
    – Package Power Limit #1…………… : 1000 Watt
    – Enable Power Limit #1……………. : 1 (enabled)
    – Package Clamping Limitation #1……. : 0 (disabled)
    – Time Window for Power Limit #1……. : 13 (20480 milli-Seconds)
    – Package Power Limit #2…………… : 1200 Watt
    – Enable Power Limit #2……………. : 1 (enabled)
    – Package Clamping Limitation #2……. : 0 (disabled)
    – Time Window for Power Limit #2……. : 13 (20480 milli-Seconds)
    – Lock…………………………… : 0 (MSR not locked)

    MSR_PKG_ENERGY_STATUS…………(0x611) : 0xF7EB98FF
    ——————————————
    – Total Energy Consumed……………. : 63467 Joules (Watt = Joules / seconds)

    MSR_PKG_POWER_INFO……………(0x614) : 0xD000000600228
    ——————————————
    – Thermal Spec Power………………. : 69 Watt
    – Minimum Power…………………… : 0
    – Maximum Power…………………… : 0
    – Maximum Time Window……………… : 0

    MSR_PP0_POWER_LIMIT…………..(0x638) : 0x1AA580
    ——————————————
    – Power Limit…………………….. : 1200 Watt
    – Enable Power Limit………………. : 1 (enabled)
    – Clamping Limitation……………… : 0 (disabled)
    – Time Window for Power Limit………. : 13 (81920 milli-Seconds)
    – Lock…………………………… : 0 (MSR not locked)

    MSR_PP0_ENERGY_STATUS…………(0x639) : 0x2E94CEA8
    ——————————————
    – Total Energy Consumed……………. : 11924 Joules (Watt = Joules / seconds)

    MSR_TURBO_ACTIVATION_RATIO…….(0x64C) : 0x0

    MSR_CONFIG_TDP_NOMINAL………..(0x648) : 0x21
    MSR_CONFIG_TDP_LEVEL1…………(0x649) : 0x60000000000000
    MSR_CONFIG_TDP_LEVEL2…………(0x64a) : 0x60000000000000
    MSR_CONFIG_TDP_CONTROL………..(0x64b) : 0x80000000
    MSR_TURBO_ACTIVATION_RATIO…….(0x64c) : 0x0
    MSR_PKGC3_IRTL……………….(0x60a) : 0x883B
    MSR_PKGC6_IRTL……………….(0x60b) : 0x8850
    MSR_PKGC7_IRTL……………….(0x60c) : 0x8857
    MSR_PKG_C2_RESIDENCY………….(0x60d) : 0x173E022F205
    MSR_PKG_C3_RESIDENCY………….(0x3f8) : 0xA9C023416D
    MSR_PKG_C6_RESIDENCY………….(0x3f9) : 0x54B5BACDC0D
    MSR_PKG_C7_RESIDENCY………….(0x3fa) : 0x0

    IA32_TSC_DEADLINE…………….(0x6E0) : 0x19236F6185EB

    CPU Ratio Info:
    ——————————————
    Base Clock Frequency (BLCK)…………. : 100 MHz
    Maximum Efficiency Ratio/Frequency…….: 16 (1600 MHz)
    Maximum non-Turbo Ratio/Frequency……..: 33 (3300 MHz)
    Maximum Turbo Ratio/Frequency…………: 37 (3700 MHz)
    P-State ratio * 100 = Frequency in MHz
    ——————————————
    CPU P-States [ (17) 22 36 ]
    CPU C3-Cores [ 4 6 7 ]
    CPU C6-Cores [ 2 3 4 5 6 7 ]
    CPU C7-Cores [ 0 1 4 6 7 ]
    CPU P-States [ (16) 17 22 25 36 ]
    CPU C3-Cores [ 0 4 5 6 7 ]
    CPU C6-Cores [ 0 2 3 4 5 6 7 ]
    CPU C7-Cores [ 0 1 2 3 4 5 6 7 ]
    CPU P-States [ 16 (17) 22 25 27 36 ]
    CPU C3-Cores [ 0 1 4 5 6 7 ]
    CPU C6-Cores [ 0 1 2 3 4 5 6 7 ]
    CPU P-States [ 16 (17) 21 22 25 27 36 ]
    CPU C3-Cores [ 0 1 2 3 4 5 6 7 ]
    CPU P-States [ 16 17 21 22 25 27 (35) 36 ]
    CPU P-States [ (16) 17 21 22 23 25 27 35 36 ]
    CPU P-States [ 16 (17) 21 22 23 25 26 27 35 36 ]
    CPU P-States [ 16 17 21 22 23 24 25 26 27 35 36 (37) ]
    CPU P-States [ 16 17 21 22 23 24 25 26 27 29 35 (36) 37 ]
    CPU P-States [ 16 17 21 22 23 24 25 26 27 29 33 35 (36) 37 ]
    CPU P-States [ 16 17 21 22 23 24 25 26 27 29 30 33 35 (36) 37 ]
    CPU P-States [ 16 17 21 22 23 24 25 26 27 29 30 31 33 (35) 36 37 ]
    CPU P-States [ 16 17 21 22 23 24 25 26 27 29 30 31 32 33 35 (36) 37 ]
    CPU P-States [ 16 17 21 22 23 24 25 26 27 29 30 31 32 33 (34) 35 36 37 ]
    CPU P-States [ (16) 17 19 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 ]
    CPU P-States [ (16) 17 18 19 21 22 23 24 25 26 27 29 30 31 32 33 34 35 36 37 ]
    CPU P-States [ 16 (17) 18 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 ]
    19 20 21 23 24 25 26 27 28 29 30 31 32 33 (34) 35 36 37 ]
    CPU P-States [ 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 (34) 35 36 37 ]

    And how to fix LFM to 1200MHz or lower such as 800MHz? Thanks.
    Cheers,
    Angel

  18. The ASUS Z10PE absolutely loves Sierra only needing FakeSMC to get to the installer … It’s thereafter the trouble starts. No Haswell-E, Broadwell-E or IvyBridge-E support, along with an old Fermi based 660Ti has me bumping into a brick wall. MP6,1 killed by GFX1 with non of the usual fixes working for me – iMac14,2 works but then there are no Frequency Vectors for me to use with my v4 Xeons and of course no iMac ever came with dual processors so I was never comfortable with it. MP5,1 works really well, but then from my understanding the MP5,1 has 0 chance of supporting XCPM, is this true ? …. At least I can use a Quadro graphics card 🙂

  19. Pike, in macOS Sierra 10.12.2 Beta (16C60b) searching in kernel I have found this:

    _ml_init_max_cpus:
    ffffff80003ffd90 55 pushq %rbp
    ffffff80003ffd91 48 89 e5 movq %rsp, %rbp
    ffffff80003ffd94 41 56 pushq %r14
    ffffff80003ffd96 53 pushq %rbx
    ffffff80003ffd97 48 83 ec 10 subq $0x10, %rsp
    ffffff80003ffd9b 9c pushfq
    ffffff80003ffd9c 5b popq %rbx
    ffffff80003ffd9d 48 81 e3 00 02 00 00 andq $0x200, %rbx
    ffffff80003ffda4 74 01 je 0xffffff80003ffda7
    ffffff80003ffda6 fa cli
    ffffff80003ffda7 8b 05 0b 75 6f 00 movl 0x6f750b(%rip), %eax
    ffffff80003ffdad 83 f8 01 cmpl $0x1, %eax
    ffffff80003ffdb0 74 56 je 0xffffff80003ffe08
    ffffff80003ffdb2 48 8d 4f ff leaq -0x1(%rdi), %rcx
    ffffff80003ffdb6 48 83 f9 3f cmpq $0x3f, %rcx
    ffffff80003ffdba 77 12 ja 0xffffff80003ffdce
    ffffff80003ffdbc 8b 0d 02 3b 61 00 movl _max_ncpus(%rip), %ecx

    what is this?
    ffffff80003ffdbc 8b 0d 02 3b 61 00 movl _max_ncpus(%rip), %ecx

    Could be useful for people for dual cpu system with more of 64 cores?

    your reboot fix patch and others are still working in this beta

    Thank you

  20. @Slice
    Do you have a idea how I can use xcpm for ivy bridge on Sierra?
    Because it seems apple removed the -xcpm flag.
    Any ideas?

    • Sorry @ Pike 😉

      I already tried different ssdt with ssdtprgen with xcpm set to 1.
      On 10.11 there was no problem with the -xcpm flag.
      Do you have a idea?

  21. Thx to your work I did it…..
    My Ivy Bridge is again working on Sierra.
    Just edited the xcpm bootstrap.
    And the reboot fix need also to be used.

    • @Ronald, you provably didn’t adjust your clock speed when you generated your SSDT. If you have overclocked your CPU, you need to tell ssdtprgen about the higher frequency, otherwise it will generate pstates for the stock clock speed of your CPU and you will effectively lose your overclock, but only in OSX. Just regenerate your SSDT with the correct frequency and that should restore your performance.

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