New repository for AppleIntelInfo.kext

I have updated AppleIntelCPUPowerManagementInfo.kext and renamed it to AppleIntelInfo.kext. It is now also much easier to get from my Github repository, and without having to pull/clone RevoBoot.

Intel GPU Register Dumper for OS X

AppleIntelInfo.kext is currently at version 1.0 and includes a new feature which I named: Intel GPU Register Dumper for OS X. This new feature is controlled by another setting in Info.plist (logIntelRegs) and it is set to True by default. The latter may be a problem for people without the IGPU being active/visible but that is something we have to figure out together.

Have a look at Yosemite DP6 with HD4600 to see what it dumps, and it dumps even more now.

Anyway. Now we don’t need to boot into Linux anymore, just to obtain the Intel GPU register data (think: intel_reg_dumper).

Warning

AppleIntelInfo.kext is brand new and may crash!!! In fact I would be surprised if it doesn’t so be prepared.

Bugs

All possible bugs (so called ‘issues’) should be filed at:

https://github.com/Piker-Alpha/AppleIntelInfo/issues

Please do not use my blog for this.

Thank you!

20 thoughts on “New repository for AppleIntelInfo.kext

  1. very nice! i got a good log from my troublesome IVB that blanks the screen. i don’t fully understand the results, would you be willing to look at the log file and give me your opinion on what it thinks is going on? if so where could i send it?

      • I’m gonna try and post it here, rather than send people to links that may die…

        PCH device……………..: 0x1C5C8086
        CPU_VGACNTRL……………: 0x8004298E
        IS_GEN5(devid) || IS_GEN6(devid) || IS_IVYBRIDGE(devid)
        PGETBL_CTL……………..: 0x00000000
        INSTDONE_I965…………..: 0x00000000
        INSTDONE_1……………..: 0x00000000
        CPU_VGACNTRL……………: 0x8004298e (disabled)
        DIGITAL_PORT_HOTPLUG_CNTRL.: 0x00000000
        RR_HW_CTL………………: 0x00000000 (low 0, high 0)
        FDI_PLL_BIOS_0………….: 0x00000000
        FDI_PLL_BIOS_1………….: 0x00000000
        FDI_PLL_BIOS_2………….: 0x00000000
        DISPLAY_PORT_PLL_BIOS_0….: 0x00000000
        DISPLAY_PORT_PLL_BIOS_1….: 0x00000000
        DISPLAY_PORT_PLL_BIOS_2….: 0x00000000
        FDI_PLL_FREQ_CTL………..: 0x00000000
        PIPEACONF………………: 0xc1000000 (enabled, active, pf-pd, rotate 0, 8bpc)
        HTOTAL_A……………….: 0x0897077f (1920 active, 2200 total)
        HBLANK_A……………….: 0x0897077f (1920 start, 2200 end)
        HSYNC_A………………..: 0x080307d7 (2008 start, 2052 end)
        VTOTAL_A……………….: 0x04640437 (1080 active, 1125 total)
        VBLANK_A……………….: 0x04640437 (1080 start, 1125 end)
        VSYNC_A………………..: 0x0440043b (1084 start, 1089 end)
        VSYNCSHIFT_A……………: 0x00000000
        PIPEASRC……………….: 0x077f0437 (1920, 1080)
        PIPEA_DATA_M1…………..: 0x7e699999 (TU 64, val 0x699999 6920601)
        PIPEA_DATA_N1…………..: 0x00800000 (val 0x800000 8388608)
        PIPEA_DATA_M2…………..: 0x00000000 (TU 1, val 0x0 0)
        PIPEA_DATA_N2…………..: 0x00000000 (val 0x0 0)
        PIPEA_LINK_M1…………..: 0x00004666 (val 0x4666 18022)
        PIPEA_LINK_N1…………..: 0x00008000 (val 0x8000 32768)
        PIPEA_LINK_M2…………..: 0x00000000 (val 0x0 0)
        PIPEA_LINK_N2…………..: 0x00000000 (val 0x0 0)
        DSPACNTR……………….: 0xd8004400 (enabled)
        DSPABASE……………….: 0x00000000
        DSPASTRIDE……………..: 0x00001e00 (120)
        DSPASURF……………….: 0x00000000
        DSPATILEOFF…………….: 0x00000000 (0, 0)
        PIPEBCONF………………: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
        HTOTAL_B……………….: 0x00000000 (1 active, 1 total)
        HBLANK_B……………….: 0x00000000 (1 start, 1 end)
        HSYNC_B………………..: 0x00000000 (1 start, 1 end)
        VTOTAL_B……………….: 0x00000000 (1 active, 1 total)
        VBLANK_B……………….: 0x00000000 (1 start, 1 end)
        VSYNC_B………………..: 0x00000000 (1 start, 1 end)
        VSYNCSHIFT_B……………: 0x00000000
        PIPEBSRC……………….: 0x00000000 (1, 1)
        PIPEB_DATA_M1…………..: 0x00000000 (TU 1, val 0x0 0)
        PIPEB_DATA_N1…………..: 0x00000000 (val 0x0 0)
        PIPEB_DATA_M2…………..: 0x00000000 (TU 1, val 0x0 0)
        PIPEB_DATA_N2…………..: 0x00000000 (val 0x0 0)
        PIPEB_LINK_M1…………..: 0x00000000 (val 0x0 0)
        PIPEB_LINK_N1…………..: 0x00000000 (val 0x0 0)
        PIPEB_LINK_M2…………..: 0x00000000 (val 0x0 0)
        PIPEB_LINK_N2…………..: 0x00000000 (val 0x0 0)
        DSPBCNTR……………….: 0x00000000 (disabled)
        DSPBBASE……………….: 0x00000000
        DSPBSTRIDE……………..: 0x00000000 (0)
        DSPBSURF……………….: 0x00000000
        DSPBTILEOFF…………….: 0x00000000 (0, 0)
        PIPECCONF………………: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
        HTOTAL_C……………….: 0x00000000 (1 active, 1 total)
        HBLANK_C……………….: 0x00000000 (1 start, 1 end)
        HSYNC_C………………..: 0x00000000 (1 start, 1 end)
        VTOTAL_C……………….: 0x00000000 (1 active, 1 total)
        VBLANK_C……………….: 0x00000000 (1 start, 1 end)
        VSYNC_C………………..: 0x00000000 (1 start, 1 end)
        VSYNCSHIFT_C……………: 0x00000000
        PIPECSRC……………….: 0x00000000 (1, 1)
        PIPEC_DATA_M1…………..: 0x00000000 (TU 1, val 0x0 0)
        PIPEC_DATA_N1…………..: 0x00000000 (val 0x0 0)
        PIPEC_DATA_M2…………..: 0x00000000 (TU 1, val 0x0 0)
        PIPEC_DATA_N2…………..: 0x00000000 (val 0x0 0)
        PIPEC_LINK_M1…………..: 0x00000000 (val 0x0 0)
        PIPEC_LINK_N1…………..: 0x00000000 (val 0x0 0)
        PIPEC_LINK_M2…………..: 0x00000000 (val 0x0 0)
        PIPEC_LINK_N2…………..: 0x00000000 (val 0x0 0)
        DSPCCNTR……………….: 0x00000000 (disabled)
        DSPCBASE……………….: 0x00000000
        DSPCSTRIDE……………..: 0x00000000 (0)
        DSPCSURF……………….: 0x00000000
        DSPCTILEOFF…………….: 0x00000000 (0, 0)
        PFA_CTL_1………………: 0x80800000 (enable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel hardcoded,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
        PFA_CTL_2………………: 0x00008000 (vscale f)
        PFA_CTL_3………………: 0x00004000 (vscale initial phase f)
        PFA_CTL_4………………: 0x00008000 (hscale f)
        PFA_WIN_POS…………….: 0x00000000 (0, 0)
        PFA_WIN_SIZE……………: 0x07800438 (1920, 1080)
        PFB_CTL_1………………: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
        PFB_CTL_2………………: 0x00007de4 (vscale f)
        PFB_CTL_3………………: 0x00003ef2 (vscale initial phase f)
        PFB_CTL_4………………: 0x00007c40 (hscale f)
        PFB_WIN_POS…………….: 0x00000000 (0, 0)
        PFB_WIN_SIZE……………: 0x00000000 (0, 0)
        PFC_CTL_1………………: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
        PFC_CTL_2………………: 0x00007de4 (vscale f)
        PFC_CTL_3………………: 0x00003ef2 (vscale initial phase f)
        PFC_CTL_4………………: 0x00007c40 (hscale f)
        PFC_WIN_POS…………….: 0x00000000 (0, 0)
        PFC_WIN_SIZE……………: 0x00000000 (0, 0)
        PCH_DREF_CONTROL………..: 0x00001402 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
        PCH_RAWCLK_FREQ…………: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
        PCH_DPLL_TMR_CFG………..: 0x0271186a
        PCH_SSC4_PARMS………….: 0x01204860
        PCH_SSC4_AUX_PARMS………: 0x000029c5
        PCH_DPLL_SEL……………: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL ))
        PCH_DPLL_ANALOG_CTL……..: 0x00008000
        PCH_DPLL_A……………..: 0xc4010001 (enable, sdvo high speed yes, mode , p2 , FPA0 P1 1, FPA1 P1 1, refclk default 120Mhz, sdvo/hdmi mul 1)
        PCH_DPLL_B……………..: 0x04800080 (disable, sdvo high speed no, mode , p2 , FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
        PCH_FPA0……………….: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
        PCH_FPA1……………….: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
        PCH_FPB0……………….: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
        PCH_FPB1……………….: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
        TRANS_HTOTAL_A………….: 0x0897077f (1920 active, 2200 total)
        TRANS_HBLANK_A………….: 0x0897077f (1920 start, 2200 end)
        TRANS_HSYNC_A…………..: 0x080307d7 (2008 start, 2052 end)
        TRANS_VTOTAL_A………….: 0x04640437 (1080 active, 1125 total)
        TRANS_VBLANK_A………….: 0x04640437 (1080 start, 1125 end)
        TRANS_VSYNC_A…………..: 0x0440043b (1084 start, 1089 end)
        TRANS_VSYNCSHIFT_A………: 0x00000000
        TRANSA_DATA_M1………….: 0x7e699999 (TU 64, val 0x699999 6920601)
        TRANSA_DATA_N1………….: 0x00800000 (val 0x800000 8388608)
        TRANSA_DATA_M2………….: 0x00000000 (TU 1, val 0x0 0)
        TRANSA_DATA_N2………….: 0x00000000 (val 0x0 0)
        TRANSA_DP_LINK_M1……….: 0x00004666 (val 0x4666 18022)
        TRANSA_DP_LINK_N1……….: 0x00008000 (val 0x8000 32768)
        TRANSA_DP_LINK_M2……….: 0x00000000 (val 0x0 0)
        TRANSA_DP_LINK_N2……….: 0x00000000 (val 0x0 0)
        TRANS_HTOTAL_B………….: 0x00000000 (1 active, 1 total)
        TRANS_HBLANK_B………….: 0x00000000 (1 start, 1 end)
        TRANS_HSYNC_B…………..: 0x00000000 (1 start, 1 end)
        TRANS_VTOTAL_B………….: 0x00000000 (1 active, 1 total)
        TRANS_VBLANK_B………….: 0x00000000 (1 start, 1 end)
        TRANS_VSYNC_B…………..: 0x00000000 (1 start, 1 end)
        TRANS_VSYNCSHIFT_B………: 0x00000000
        TRANSB_DATA_M1………….: 0x00000000 (TU 1, val 0x0 0)
        TRANSB_DATA_N1………….: 0x00000000 (val 0x0 0)
        TRANSB_DATA_M2………….: 0x00000000 (TU 1, val 0x0 0)
        TRANSB_DATA_N2………….: 0x00000000 (val 0x0 0)
        TRANSB_DP_LINK_M1……….: 0x00000000 (val 0x0 0)
        TRANSB_DP_LINK_N1……….: 0x00000000 (val 0x0 0)
        TRANSB_DP_LINK_M2……….: 0x00000000 (val 0x0 0)
        TRANSB_DP_LINK_N2……….: 0x00000000 (val 0x0 0)
        TRANS_HTOTAL_C………….: 0x00000000 (1 active, 1 total)
        TRANS_HBLANK_C………….: 0x00000000 (1 start, 1 end)
        TRANS_HSYNC_C…………..: 0x00000000 (1 start, 1 end)
        TRANS_VTOTAL_C………….: 0x00000000 (1 active, 1 total)
        TRANS_VBLANK_C………….: 0x00000000 (1 start, 1 end)
        TRANS_VSYNC_C…………..: 0x00000000 (1 start, 1 end)
        TRANS_VSYNCSHIFT_C………: 0x00000000
        TRANSC_DATA_M1………….: 0x00000000 (TU 1, val 0x0 0)
        TRANSC_DATA_N1………….: 0x00000000 (val 0x0 0)
        TRANSC_DATA_M2………….: 0x00000000 (TU 1, val 0x0 0)
        TRANSC_DATA_N2………….: 0x00000000 (val 0x0 0)
        TRANSC_DP_LINK_M1……….: 0x00000000 (val 0x0 0)
        TRANSC_DP_LINK_N1……….: 0x00000000 (val 0x0 0)
        TRANSC_DP_LINK_M2……….: 0x00000000 (val 0x0 0)
        TRANSC_DP_LINK_N2……….: 0x00000000 (val 0x0 0)
        TRANSACONF……………..: 0xc0000000 (enable, active, progressive)
        TRANSBCONF……………..: 0x00000000 (disable, inactive, progressive)
        TRANSCCONF……………..: 0x00000000 (disable, inactive, progressive)
        FDI_TXA_CTL…………….: 0x800c4f02 (enable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
        FDI_TXB_CTL…………….: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
        FDI_TXC_CTL…………….: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
        FDI_RXA_CTL…………….: 0x80082f50 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc enable, FE ecc enable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
        FDI_RXB_CTL…………….: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
        FDI_RXC_CTL…………….: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
        DPAFE_BMFUNC……………: 0x0001d233
        DPAFE_DL_IREFCAL0……….: 0x00d22bdc
        DPAFE_DL_IREFCAL1……….: 0x00d22bdc
        DPAFE_DP_IREFCAL………..: 0x80d2218c
        PCH_DSPCLK_GATE_D……….: 0x10000000
        PCH_DSP_CHICKEN1………..: 0x00000000
        PCH_DSP_CHICKEN2………..: 0x02000000
        PCH_DSP_CHICKEN3………..: 0x00000024
        FDI_RXA_MISC……………: 0x00200080 (FDI Delay 128)
        FDI_RXB_MISC……………: 0x00200080 (FDI Delay 128)
        FDI_RXC_MISC……………: 0x00200080 (FDI Delay 128)
        FDI_RXA_TUSIZE1…………: 0x7e000000
        FDI_RXA_TUSIZE2…………: 0x7e000000
        FDI_RXB_TUSIZE1…………: 0x7e000000
        FDI_RXB_TUSIZE2…………: 0x7e000000
        FDI_RXC_TUSIZE1…………: 0x7e000000
        FDI_RXC_TUSIZE2…………: 0x7e000000
        FDI_PLL_CTL_1…………..: 0x7e000000
        FDI_PLL_CTL_2…………..: 0x7e000000
        FDI_RXA_IIR…………….: 0x00000700
        FDI_RXA_IMR…………….: 0x00000000
        FDI_RXB_IIR…………….: 0x00000000
        FDI_RXB_IMR…………….: 0x000008ff
        PCH_ADPA……………….: 0x00c40000 (disabled, transcoder A, -hsync, -vsync)
        HDMIB………………….: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
        HDMIC………………….: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
        HDMID………………….: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
        PCH_LVDS……………….: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
        CPU_eDP_A………………: 0x00000018
        PCH_DP_B……………….: 0x00000000
        PCH_DP_C……………….: 0x00000000
        PCH_DP_D……………….: 0x82480304
        TRANS_DP_CTL_A………….: 0xc0040000 (enable port D 8bpc -vsync -hsync)
        TRANS_DP_CTL_B………….: 0x60000018 (disable port none 8bpc +vsync +hsync)
        TRANS_DP_CTL_C………….: 0x60000018 (disable port none 8bpc +vsync +hsync)
        BLC_PWM_CPU_CTL2………..: 0x80000000 (enable 1, pipe A)
        BLC_PWM_CPU_CTL…………: 0x00001312 (cycle 4882)
        BLC_PWM_PCH_CTL1………..: 0xa0000000 (enable 1, override 0, inverted polarity 1)
        BLC_PWM_PCH_CTL2………..: 0x13121312 (freq 4882, cycle 4882)
        PCH_PP_STATUS…………..: 0xc0000008 (on, ready, sequencing idle)
        PCH_PP_CONTROL………….: 0x00000007 (blacklight enabled, power down on reset, panel on)
        PCH_PP_ON_DELAYS………..: 0xc7d0000a
        PCH_PP_OFF_DELAYS……….: 0x01f407d0
        PCH_PP_DIVISOR………….: 0x00186906
        PORT_DBG……………….: 0x0000f00f (HW DRRS off)
        RC6_RESIDENCY_TIME………: 0x0007a8bb
        RC6p_RESIDENCY_TIME……..: 0x26ea843b
        RC6pp_RESIDENCY_TIME…….: 0x00000000
        IS_GEN6(devid) || IS_GEN7(devid)
        FENCE START 0…………..: 0x00000001
        FENCE END 0…………….: 0x00fff03b
        FENCE START 1…………..: 0x00000000
        FENCE END 1…………….: 0x00000000
        FENCE START 2…………..: 0x00000000
        FENCE END 2…………….: 0x00000000
        FENCE START 3…………..: 0x00000000
        FENCE END 3…………….: 0xfffff3ff
        FENCE START 4…………..: 0x00000000
        FENCE END 4…………….: 0x00000000
        FENCE START 5…………..: 0x00000000
        FENCE END 5…………….: 0x00000000
        FENCE START 6…………..: 0x00000000
        FENCE END 6…………….: 0x00000000
        FENCE START 7…………..: 0x00000000
        FENCE END 7…………….: 0x00000000
        FENCE START 8…………..: 0x00000000
        FENCE END 8…………….: 0x00000000
        FENCE START 9…………..: 0x00000000
        FENCE END 9…………….: 0x00000000
        FENCE START 10………….: 0x00000000
        FENCE END 10……………: 0x00000000
        FENCE START 11………….: 0x00000000
        FENCE END 11……………: 0x00000000
        FENCE START 12………….: 0x00000000
        FENCE END 12……………: 0x00000000
        FENCE START 13………….: 0x00000000
        FENCE END 13……………: 0x00000000
        FENCE START 14………….: 0x00000000
        FENCE END 14……………: 0x00000000
        FENCE START 15………….: 0x00000000
        FENCE END 15……………: 0x00000000
        FENCE START 16………….: 0x00000000
        FENCE END 16……………: 0x00000000
        FENCE START 17………….: 0x00000000
        FENCE END 17……………: 0x00000000
        FENCE START 18………….: 0x00000000
        FENCE END 18……………: 0x00000000
        FENCE START 19………….: 0x00000000
        FENCE END 19……………: 0x00000000
        FENCE START 20………….: 0x00000000
        FENCE END 20……………: 0x00000000
        FENCE START 20………….: 0x00000000
        FENCE END 20……………: 0x00000000
        FENCE START 21………….: 0x00000000
        FENCE END 21……………: 0x00000000
        FENCE START 22………….: 0x00000000
        FENCE END 22……………: 0x00000000
        FENCE START 23………….: 0x00000000
        FENCE END 23……………: 0x00000000
        FENCE START 24………….: 0x00000000
        FENCE END 24……………: 0x00000000
        FENCE START 25………….: 0x00000000
        FENCE END 25……………: 0x00000000
        FENCE START 26………….: 0x00000000
        FENCE END 26……………: 0x00000000
        FENCE START 27………….: 0x00000000
        FENCE END 27……………: 0x00000000
        FENCE START 28………….: 0x00000000
        FENCE END 28……………: 0x00000000
        FENCE START 29………….: 0x00000000
        FENCE END 29……………: 0x00000000
        FENCE START 30………….: 0x00000000
        FENCE END 30……………: 0x00000000
        FENCE START 31………….: 0x00000000
        FENCE END 31……………: 0x00000000
        GEN6_RP_CONTROL…………: 0x00000000 (disabled)
        GEN6_RPNSWREQ…………..: 0x00000000
        GEN6_RP_DOWN_TIMEOUT…….: 0x00000000
        GEN6_RP_INTERRUPT_LIMITS…: 0x00000000
        GEN6_RP_UP_THRESHOLD…….: 0x00000000
        GEN6_RP_UP_EI…………..: 0x00000000
        GEN6_RP_DOWN_EI…………: 0x00000000
        GEN6_RP_IDLE_HYSTERSIS…..: 0x00000000
        GEN6_RC_STATE…………..: 0x00000000
        GEN6_RC_CONTROL…………: 0x00000000
        GEN6_RC1_WAKE_RATE_LIMIT…: 0x00000000
        GEN6_RC6_WAKE_RATE_LIMIT…: 0x00000000
        GEN6_RC_EVALUATION_INTERVAL: 0x00000000
        GEN6_RC_IDLE_HYSTERSIS…..: 0x00000000
        GEN6_RC_SLEEP…………..: 0x00000000
        GEN6_RC1e_THRESHOLD……..: 0x00000000
        GEN6_RC6_THRESHOLD………: 0x00000000
        GEN6_RC_VIDEO_FREQ………: 0x00000000
        GEN6_PMIER……………..: 0x00000030
        GEN6_PMIMR……………..: 0xffffffcf
        GEN6_PMINTRMSK………….: 0x00000000
      • This is with AppleIntelFramebufferCapri.kext correct?
        What frame buffer are you using?
        Did you change it, if yes publish it here as well.

        I should add a note in AppleIntelFramebufferAzul.sh for AppleIntelFramebufferCapri.kext support, by setting gDataBytes to 200 and running:

        ./AppleIntelFramebufferAzul.sh dump /S*/L*/E*/AppleIntelFramebufferC*/C*/M*/A*

      • Yep, Capri. Framebuffer ‘5’ but all suitable framebuffers do the same thing. I have tried various modifications to no avail. The display is detected okay I can see it via screen sharing. The problem exactly is that there are two outputs on the computer, eDP and VGA. Using framebuffer 5 or A etc the eDP outputs to pipe 00 but this actually goes to the VGA port, if I mod the framebuffer to support VGA then that is also detected but outputs to pipe 01. So you get garbled on both displays then. When I thought I needed to achieve was to get the eDP to output to pipe01 but this seems impossible to manually control. I have a bios unlock tool, but nothing seems to mention FDI, there are options for B, C and D to mux or not, but I don’t know what that is.

      • Has it ever worked? If yes, which version of OS X was that? In that case a dump would also be handy.

        Also. We need to compare the output with that of the intel_reg_dumper to see if all registers are dumped, if not then we should find the source code so that I can add the missing pieces.

      • Never worked. From 10.7 when it was introduced right up to yosemite. Exact same issue. I’ll Run up a version of Ubuntu and get a reg dump from that while it’s working.

      • I’ve looked for obvious (to me) differences side by side, PFA_CTL_1 is enabled on OS X, disabled in Ubuntu. I don’t really see anything else.

        I don’t know what determines the pipe ID assignment. Hardware layout/bios/apple driver.

  2. here is the output on the same machine running ubuntu 14.04, display works correctly.

    PGETBL_CTL: 0x00000000
    GEN6_INSTDONE_1: 0xfffffffe
    GEN6_INSTDONE_2: 0x00000000
    CPU_VGACNTRL: 0x80000000 (disabled)
    DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
    RR_HW_CTL: 0x00000000 (low 0, high 0)
    FDI_PLL_BIOS_0: 0x00000000
    FDI_PLL_BIOS_1: 0x00000000
    FDI_PLL_BIOS_2: 0x00000000
    DISPLAY_PORT_PLL_BIOS_0: 0x00000000
    DISPLAY_PORT_PLL_BIOS_1: 0x00000000
    DISPLAY_PORT_PLL_BIOS_2: 0x00000000
    FDI_PLL_FREQ_CTL: 0x00000000
    PIPEACONF: 0xc0000050 (enabled, active, pf-pd, rotate 0, 6bpc)
    HTOTAL_A: 0x0897077f (1920 active, 2200 total)
    HBLANK_A: 0x0897077f (1920 start, 2200 end)
    HSYNC_A: 0x080307d7 (2008 start, 2052 end)
    VTOTAL_A: 0x04640437 (1080 active, 1125 total)
    VBLANK_A: 0x04640437 (1080 start, 1125 end)
    VSYNC_A: 0x0440043b (1084 start, 1089 end)
    VSYNCSHIFT_A: 0x00000000
    PIPEASRC: 0x077f0437 (1920, 1080)
    PIPEA_DATA_M1: 0x7e4f3333 (TU 64, val 0x4f3333 5190451)
    PIPEA_DATA_N1: 0x00800000 (val 0x800000 8388608)
    PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
    PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
    PIPEA_LINK_M1: 0x00046666 (val 0x46666 288358)
    PIPEA_LINK_N1: 0x00080000 (val 0x80000 524288)
    PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
    PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
    DSPACNTR: 0xd8004400 (enabled)
    DSPABASE: 0x00000000
    DSPASTRIDE: 0x00001e00 (120)
    DSPASURF: 0x01064000
    DSPATILEOFF: 0x00000000 (0, 0)
    PIPEBCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
    HTOTAL_B: 0x00000000 (1 active, 1 total)
    HBLANK_B: 0x00000000 (1 start, 1 end)
    HSYNC_B: 0x00000000 (1 start, 1 end)
    VTOTAL_B: 0x00000000 (1 active, 1 total)
    VBLANK_B: 0x00000000 (1 start, 1 end)
    VSYNC_B: 0x00000000 (1 start, 1 end)
    VSYNCSHIFT_B: 0x00000000
    PIPEBSRC: 0x00000000 (1, 1)
    PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
    PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
    PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
    PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
    PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
    PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
    PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
    PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
    DSPBCNTR: 0x00004000 (disabled)
    DSPBBASE: 0x00000000
    DSPBSTRIDE: 0x00000000 (0)
    DSPBSURF: 0x00000000
    DSPBTILEOFF: 0x00000000 (0, 0)
    PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
    HTOTAL_C: 0x00000000 (1 active, 1 total)
    HBLANK_C: 0x00000000 (1 start, 1 end)
    HSYNC_C: 0x00000000 (1 start, 1 end)
    VTOTAL_C: 0x00000000 (1 active, 1 total)
    VBLANK_C: 0x00000000 (1 start, 1 end)
    VSYNC_C: 0x00000000 (1 start, 1 end)
    VSYNCSHIFT_C: 0x00000000
    PIPECSRC: 0x00000000 (1, 1)
    PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
    PIPEC_DATA_N1: 0x00000000 (val 0x0 0)
    PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
    PIPEC_DATA_N2: 0x00000000 (val 0x0 0)
    PIPEC_LINK_M1: 0x00000000 (val 0x0 0)
    PIPEC_LINK_N1: 0x00000000 (val 0x0 0)
    PIPEC_LINK_M2: 0x00000000 (val 0x0 0)
    PIPEC_LINK_N2: 0x00000000 (val 0x0 0)
    DSPCCNTR: 0x00004000 (disabled)
    DSPCBASE: 0x00000000
    DSPCSTRIDE: 0x00000000 (0)
    DSPCSURF: 0x00000000
    DSPCTILEOFF: 0x00000000 (0, 0)
    PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
    PFA_CTL_2: 0x00007de4 (vscale 0.983521)
    PFA_CTL_3: 0x00003ef2 (vscale initial phase 0.491760)
    PFA_CTL_4: 0x00007c40 (hscale 0.970703)
    PFA_WIN_POS: 0x00000000 (0, 0)
    PFA_WIN_SIZE: 0x00000000 (0, 0)
    PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
    PFB_CTL_2: 0x00007de4 (vscale 0.983521)
    PFB_CTL_3: 0x00003ef2 (vscale initial phase 0.491760)
    PFB_CTL_4: 0x00007c40 (hscale 0.970703)
    PFB_WIN_POS: 0x00000000 (0, 0)
    PFB_WIN_SIZE: 0x00000000 (0, 0)
    PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
    PFC_CTL_2: 0x00007de4 (vscale 0.983521)
    PFC_CTL_3: 0x00003ef2 (vscale initial phase 0.491760)
    PFC_CTL_4: 0x00007c40 (hscale 0.970703)
    PFC_WIN_POS: 0x00000000 (0, 0)
    PFC_WIN_SIZE: 0x00000000 (0, 0)
    PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
    PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
    PCH_DPLL_TMR_CFG: 0x0271186a
    PCH_SSC4_PARMS: 0x01204860
    PCH_SSC4_AUX_PARMS: 0x000029c5
    PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null)))
    PCH_DPLL_ANALOG_CTL: 0x00008000
    PCH_DPLL_A: 0xc4020002 (enable, sdvo high speed yes, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
    PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
    PCH_FPA0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
    PCH_FPA1: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
    PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
    PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
    TRANS_HTOTAL_A: 0x0897077f (1920 active, 2200 total)
    TRANS_HBLANK_A: 0x0897077f (1920 start, 2200 end)
    TRANS_HSYNC_A: 0x080307d7 (2008 start, 2052 end)
    TRANS_VTOTAL_A: 0x04640437 (1080 active, 1125 total)
    TRANS_VBLANK_A: 0x04640437 (1080 start, 1125 end)
    TRANS_VSYNC_A: 0x0440043b (1084 start, 1089 end)
    TRANS_VSYNCSHIFT_A: 0x00000000
    TRANSA_DATA_M1: 0x7e420000 (TU 64, val 0x420000 4325376)
    TRANSA_DATA_N1: 0x00800000 (val 0x800000 8388608)
    TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
    TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
    TRANSA_DP_LINK_M1: 0x0003aaaa (val 0x3aaaa 240298)
    TRANSA_DP_LINK_N1: 0x00040000 (val 0x40000 262144)
    TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
    TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
    TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
    TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
    TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
    TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
    TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
    TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
    TRANS_VSYNCSHIFT_B: 0x00000000
    TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
    TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
    TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
    TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
    TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
    TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
    TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
    TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
    TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
    TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
    TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
    TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
    TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
    TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
    TRANS_VSYNCSHIFT_C: 0x00000000
    TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
    TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
    TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
    TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
    TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
    TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
    TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
    TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
    TRANSACONF: 0xc0000000 (enable, active, progressive)
    TRANSBCONF: 0x00000000 (disable, inactive, progressive)
    TRANSCCONF: 0x00000000 (disable, inactive, progressive)
    FDI_TXA_CTL: 0x800c4b00 (enable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
    FDI_TXB_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
    FDI_TXC_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
    FDI_RXA_CTL: 0x8c0a2b50 (enable, train pattern not train, port width X2, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc enable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
    FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
    FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
    FDI_RXA_MISC: 0x00200090 (FDI Delay 144)
    FDI_RXB_MISC: 0x00200080 (FDI Delay 128)
    FDI_RXC_MISC: 0x00200080 (FDI Delay 128)
    FDI_RXA_TUSIZE1: 0x7e000000
    FDI_RXA_TUSIZE2: 0x7e000000
    FDI_RXB_TUSIZE1: 0x7e000000
    FDI_RXB_TUSIZE2: 0x7e000000
    FDI_RXC_TUSIZE1: 0x7e000000
    FDI_RXC_TUSIZE2: 0x7e000000
    FDI_PLL_CTL_1: 0x7e000000
    FDI_PLL_CTL_2: 0x7e000000
    FDI_RXA_IIR: 0x00000000
    FDI_RXA_IMR: 0x000008ff
    FDI_RXB_IIR: 0x00000000
    FDI_RXB_IMR: 0x000008ff
    PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
    HDMIB: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
    HDMIC: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
    HDMID: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
    PCH_LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
    CPU_eDP_A: 0x00000018
    PCH_DP_B: 0x00000000
    PCH_DP_C: 0x00000000
    PCH_DP_D: 0x80180304
    TRANS_DP_CTL_A: 0xc0040400 (enable port D 6bpc -vsync -hsync)
    TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
    TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
    BLC_PWM_CPU_CTL2: 0x80000000
    BLC_PWM_CPU_CTL: 0x00001312
    BLC_PWM_PCH_CTL1: 0xa0000000
    BLC_PWM_PCH_CTL2: 0x13121312
    PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
    PCH_PP_CONTROL: 0xabcd0007 (blacklight enabled, power down on reset, panel on)
    PCH_PP_ON_DELAYS: 0xc7d0000a
    PCH_PP_OFF_DELAYS: 0x01f407d0
    PCH_PP_DIVISOR: 0x00186906
    PORT_DBG: 0x00007007 (HW DRRS off)
    RC6_RESIDENCY_TIME: 0x02c4c061
    RC6p_RESIDENCY_TIME: 0x375c7428
    RC6pp_RESIDENCY_TIME: 0x00103b1f
    GEN6_RP_CONTROL: 0x00000d92 (enabled)
    GEN6_RPNSWREQ: 0x0e000000
    GEN6_RP_DOWN_TIMEOUT: 0x0000c350
    GEN6_RP_INTERRUPT_LIMITS: 0x16070000
    GEN6_RP_UP_THRESHOLD: 0x00002e18
    GEN6_RP_UP_EI: 0x000030d4
    GEN6_RP_DOWN_EI: 0x000061a8
    GEN6_RP_IDLE_HYSTERSIS: 0x0000000a
    GEN6_RC_STATE: 0x00000000
    GEN6_RC_CONTROL: 0x88060000
    GEN6_RC1_WAKE_RATE_LIMIT: 0x03e80000
    GEN6_RC6_WAKE_RATE_LIMIT: 0x0028001e
    GEN6_RC_EVALUATION_INTERVAL: 0x0001e848
    GEN6_RC_IDLE_HYSTERSIS: 0x00000019
    GEN6_RC_SLEEP: 0x00000000
    GEN6_RC1e_THRESHOLD: 0x000003e8
    GEN6_RC6_THRESHOLD: 0x0001e848
    GEN6_RC_VIDEO_FREQ: 0x00000000
    GEN6_PMIER: 0x00000070
    GEN6_PMIMR: 0xffffff8f
    GEN6_PMINTRMSK: 0x0000000a

  3. Pike also for the this piece of fine coding, again many thanks.
    While trying it out I ran into the following strange situation, normally I have the following states:
    AICPUPMI: CPU P-States [ (8) 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 ] iGPU P-States [ 4 (15) 26 ]
    But when I was changing the SMBIOS model identifier into MacPro5,1 and left the serial etc. as was a iMac14,1 I suddenly got a lot more iGPU states. To bad I somehow can’t reproduce this.
    What is normal to have as iGPU states?

    • Remember this; The number of idle states is not that important, as long as it works, and that number can even be different on two setups with the same processor so it is hard to tell what you should see.

  4. Hello Pike
    I have Intel(R) Core(TM) i5-2500 CPU @ 3.30GHz and i don not know if speed stepping works for me. Here’s my result and kindly let me know if it works or not.. Thank You!!!

    Edit by Pike: Dump removed

  5. Is AppleIntelInfo.kext loadable and unloadable on the fly using kextload and kextunload? I attempted to load it, but got a permissions error:

    AppleIntelInfo.kext failed to load – (libkern/kext) authentication failure (file ownership/permissions); check the system/kernel logs for errors or try kextutil(8).

    I tried making it root-owned, which made no difference.

    • Yes it is, but you need to set the right permissions and file ownership with:

      cd /System/Library/Extensions
      sudo chown -R root:wheel AppleIntelInfo.kext
      sudo chmod -R 744 AppleIntelInfo.kext

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